High-level test synthesis for delay fault testability. - Sying-Jyan Wang; Tung-Hua Yeh (DATE, 2007)

Test Data Compression for Minimum Test Application Time. - Po-Chang Tsai; Sying-Jyan Wang; Ching-Hung Lin; Tung-Hua Yeh (J. Inf. Sci. Eng., 2007)

High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability. - Sying-Jyan Wang; Tung-Hua Yeh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Thermal Safe High Level Test Synthesis for Hierarchical Testability. - Tung-Hua Yeh; Sying-Jyan Wang (Asian Test Symposium, 2010)

Power-Aware High-Level Synthesis With Clock Skew Management. - Tung-Hua Yeh; Sying-Jyan Wang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications. - Jyu-Yuan Lai; Chih-Tsun Huang; Ting-Shuo Hsu; Jing-Jia Liou; Tung-Hua Yeh; Liang-Chia Cheng; Juin-Ming Lu (SoCC, 2014)

High-level low-power system design optimization. - David Pursley; Tung-Hua Yeh (VLSI-DAT, 2017)