DVFS Considering Spatial Correlation Timing and Process-Voltage-Temperature Variations. - Tung-Liang Lin; Sao-Jie Chen (SoCC, 2020)

A Platform of Resynthesizing a Clock Architecture Into Power-and-Area Effective Clock Trees. - Tung-Liang Lin; Sao-Jie Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

An Error Resilient Design Platform for Aggressively Reducing Power, Area and Routing Congestion. - Tung-Liang Lin; Sao-Jie Chen (ISQED, 2021)