Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements. - Tung Thanh Hoang; Magnus Själander; Per Larsson-Edefors (IPDPS, 2009)

High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture. - Tung Thanh Hoang; Magnus Själander; Per Larsson-Edefors (SoCC, 2009)

Design space exploration for an embedded processor with flexible datapath interconnect. - Tung Thanh Hoang; Ulf Jalmbrant; Erik der Hagopian; Kasyab P. Subramaniyan; Magnus Själander; Per Larsson-Edefors (ASAP, 2010)

Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor. - Muhammad Waqar Azhar; Tung Thanh Hoang; Per Larsson-Edefors (DSD, 2010)

A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit. - Tung Thanh Hoang; Magnus Själander; Per Larsson-Edefors (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Viterbi Accelerator for Embedded Processor Datapaths. - Muhammad Waqar Azhar; Magnus Själander; Hasan Ali; Akshay Vijayashekar; Tung Thanh Hoang; Kashan Khurshid Ansari; Per Larsson-Edefors (ASAP, 2012)

Data-Width-Driven Power Gating of Integer Arithmetic Circuits. - Tung Thanh Hoang; Per Larsson-Edefors (ISVLSI, 2012)

Performance and energy limits of a processor-integrated FFT accelerator. - Tung Thanh Hoang; Amirali Shambayati; Calvin Deutschbein; Henry Hoffmann; Andrew A. Chien (HPEC, 2014)

Does arithmetic logic dominate data movement? a systematic comparison of energy-efficiency for FFT accelerators. - Tung Thanh Hoang; Amirali Shambayati; Henry Hoffmann; Andrew A. Chien (ASAP, 2015)

Fast support for unstructured data processing: the unified automata processor. - Yuanwei Fang; Tung Thanh Hoang; Michela Becchi; Andrew A. Chien (MICRO, 2015)

10x10: A Case Study in Highly-Programmable and Energy-Efficient Heterogeneous Federated Architecture. - Andrew A. Chien; Tung Thanh Hoang; Dilip P. Vasudevan; Yuanwei Fang; Amirali Shambayati (SIGARCH Comput. Archit. News, 2015)

A Data Layout Transformation (DLT) accelerator: Architectural support for data movement optimization in accelerated-centric heterogeneous systems. - Tung Thanh Hoang; Amirali Shambayati; Andrew A. Chien (DATE, 2016)

An In-Flash Binary Neural Network Accelerator with SLC NAND Flash Array. - Won Ho Choi; Pi-Feng Chiu; Wen Ma; Gertjan Hemink; Tung Thanh Hoang; Martin Lueker-Boden; Zvonimir Bandic (ISCAS, 2020)

Effect of OTS Selector Reliabilities on NVM Crossbar-based Neuromorphic Training. - Wen Ma; Tung Thanh Hoang; Brian Hoskins; Matthew W. Daniels; Jabez J. McClelland; Yutong Gao 003; Gina C. Adam; Martin Lueker-Boden (IRPS, 2022)