CMOS on-chip ESD protection design with substrate-triggering technique. - Ming-Dou Ker; Tung-Yang Chen; Chung-Yu Wu (ICECS, 1998)

ESD buses for whole-chip ESD protection. - Ming-Dou Ker; Hun-Hsien Chang; Tung-Yang Chen (ISCAS (1), 1999)

Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications. - Ming-Dou Ker; Tung-Yang Chen; Chung-Yu Wu; Hun-Hsien Chang (ISCAS, 2000)

ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications. - Ming-Dou Ker; Tung-Yang Chen; Chung-Yu Wu; Hun-Hsien Chang (IEEE J. Solid State Circuits, 2000)

Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes. - Ming-Dou Ker; Tung-Yang Chen (ISCAS (4), 2001)

ESD protection design in a 0.18-um salicide CMOS technology by using substrate-triggered technique. - Ming-Dou Ker; Tung-Yang Chen; Chung-Yu Win (ISCAS (4), 2001)

Design on ESD Protection Circuit with Very Low and Constant Input Capacitance. - Tung-Yang Chen; Ming-Dou Ker (ISQED, 2001)

Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process. - Ming-Dou Ker; Wen-Yu Lo; Tung-Yang Chen; Howard Tang; S.-S. Chen; Mu-Chun Wang (ISQED, 2001)

On-chip ESD protection design by using polysilicon diodes in CMOS process. - Ming-Dou Ker; Tung-Yang Chen; Tai-Ho Wang; Chung-Yu Wu (IEEE J. Solid State Circuits, 2001)

Substrate-triggered ESD protection circuit without extra process modification. - Ming-Dou Ker; Tung-Yang Chen (IEEE J. Solid State Circuits, 2003)