Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash. - Shantanu Rajwade; Wing-Kei S. Yu; Sarah Q. Xu; Tuo-Hung Hou; G. Edward Suh; Edwin Kan (SoCC, 2010)

Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. - Pai-Yu Chen; Binbin Lin; I-Ting Wang; Tuo-Hung Hou; Jieping Ye; Sarma B. K. Vrudhula; Jae-sun Seo; Yu Cao 001; Shimeng Yu (ICCAD, 2015)

Crossbar array of selector-less TaOx/TiO2 bilayer RRAM. - Chun-Tse Chou; Boris Hudec; Chung-Wei Hsu; Wei-Li Lai; Chih-Cheng Chang; Tuo-Hung Hou (Microelectron. Reliab., 2015)

3D resistive RAM cell design for high-density storage class memory - a review. - Boris Hudec; Chung-Wei Hsu; I-Ting Wang; Wei-Li Lai; Che-Chia Chang; Taifang Wang; Karol Fröhlich; Chia-Hua Ho; Chen-Hsi Lin; Tuo-Hung Hou (Sci. China Inf. Sci., 2016)

SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices. - Sandeep Kaur Kingra; Vivek Parmar; Che-Chia Chang; Boris Hudec; Tuo-Hung Hou; Manan Suri (CoRR, 2018)

Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse. - Chih-Cheng Chang; Pin-Chun Chen; Teyuh Chou; I-Ting Wang; Boris Hudec; Che-Chia Chang; Chia-Ming Tsai; Tian-Sheuan Chang; Tuo-Hung Hou (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

Optimizing Incremental Step Pulse Programming for RRAM Through Device-Circuit Co-Design. - Jen-Chieh Liu; Tzu-Yun Wu; Tuo-Hung Hou (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge. - Chih-Cheng Chang; Ming-Hung Wu; Jia-Wei Lin; Chun-Hsien Li; Vivek Parmar; Heng-Yuan Lee; Jeng-Hua Wei; Shyh-Shyuan Sheu; Manan Suri; Tian-Sheuan Chang; Tuo-Hung Hou (DAC, 2019)

Phase and Carrier Polarity Control of Sputtered MoTe2 by Plasma-induced Defect Engineering. - Chih-Pin Lin; Hao-Hua Hsu; Tuo-Hung Hou (DRC, 2020)

Methodology for Realizing VMM with Binary RRAM Arrays: Experimental Demonstration of Binarized-ADALINE using OxRAM Crossbar. - Sandeep Kaur Kingra; Vivek Parmar; Shubham Negi; Sufyan Khan; Boris Hudec; Tuo-Hung Hou; Manan Suri (ISCAS, 2020)

A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration. - Chih-Sheng Lin; Fu-Cheng Tsai; Jian-Wei Su; Sih-Han Li; Tian-Sheuan Chang; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang; Chih-I Wu; Tuo-Hung Hou (A-SSCC, 2021)

Progress and Benchmark of Spiking Neuron Devices and Circuits. - Fu-Xiang Liang; I-Ting Wang; Tuo-Hung Hou (Adv. Intell. Syst., 2021)

An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications. - Chi Liu; Shao-Tzu Li; Tong-Lin Pan; Cheng-En Ni; Yun Sung; Chia-Lin Hu; Kang-Yu Chang; Tuo-Hung Hou; Tian-Sheuan Chang; Shyh-Jye Jou (VLSI-DAT, 2022)

A 4K-400K Wide Operating-Temperature-Range MRAM Technology with Ultrathin Composite Free Layer and Magnesium Spacer. - Ming-Chun Hong; Yao-Jen Chang; Yu-Chen Hsin; Liang-Ming Liu; Kuan-Ming Chen; Yi-Hui Su; Guan-Long Chen; Shan-Yi Yang; I-Jung Wang; Sk. Ziaur Rahaman; Hsin-Han Lee; Shih-Ching Chiu; et al. (VLSI Technology and Circuits, 2022)

Hardware-Robust In-RRAM-Computing for Object Detection. - Yu-Hsiang Chiang; Cheng-En Ni; Yun Sung; Tuo-Hung Hou; Tian-Sheuan Chang; Shyh-Jye Jou (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Two-dimensional materials for artificial synapses: toward a practical application. - I-Ting Wang; Chih-Cheng Chang; Yen-Yu Chen; Yi-Shin Su; Tuo-Hung Hou (Neuromorph. Comput. Eng., 2022)

FPCIM: A Fully-Parallel Robust ReRAM CIM Processor for Edge AI Devices. - Yan-Cheng Guo; Wei-Tien Lin; Tuo-Hung Hou; Tian-Sheuan Chang (ISCAS, 2023)

U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory. - Ming-Hung Wu; Ming-Chun Hong; Ching Shih; Yao-Jen Chang; Yu-Chen Hsin; Shih-Ching Chiu; Kuan-Ming Chen; Yi-Hui Su; Chih-Yao Wang; Shan-Yi Yang; Guan-Long Chen; Hsin-Han Lee; et al. (VLSI Technology and Circuits, 2023)

A Multi-Bit Near-RRAM based Computing Macro with Highly Computing Parallelism for CNN Application. - Kuan-Chih Lin; Hao Zuo; Hsiang-Yu Wang; Yuan-Ping Huang; Ci-Hao Wu; Yan-Cheng Guo; Shyh-Jye Jou; Tuo-Hung Hou; Tian-Sheuan Chang (DATE, 2024)

Bit-Cost-Scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gate-Around and Channel-Around IGZO FETs. - Feng-Min Lee; Po-Hao Tseng; Yu-Yu Lin; Yu-Hsuan Lin; Wei-Lun Weng; Nei-Chih Lin; Po-Jung Sung; Chien-Ting Wu; Chih-Chao Yang; Wen-Fa Wu; Chang-Hong Shen; Tuo-Hung Hou; et al. (VLSI Technology and Circuits, 2024)

Empowering Local Differential Privacy: A 5718 TOPS/W Analog PUF-Based In-Memory Encryption Macro for Dynamic Edge Security. - Chih-Sheng Lin; Bo-Cheng Chiou; Yin-Jia Yang; Jian-Wei Su; Kuo-Hua Tseng; Yun-Ting Ho; Chih-Ming Lai; Sih-Han Li; Tian-Sheuan Chang; Shan-Ming Chang; Shyh-Shyuan Sheu; Wei-Chung Lo; et al. (VLSI Technology and Circuits, 2024)

3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25×33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi. - Bo-Jheng Shih; Yu-Ming Pan; Hao-Tung Chung; Chieh-Ling Lee; I-Chun Hsieh; Nein-Chih Lin; Chih-Chao Yang; Po-Tsang Huang; Hung-Ming Chen; Chiao-Yen Wang; Huan-Yu Chiu; Huang-Chung Cheng; et al. (VLSI Technology and Circuits, 2024)

Roadmap to Neuromorphic Computing with Emerging Technologies. - Adnan Mehonic; Daniele Ielmini; Kaushik Roy 001; Onur Mutlu; Shahar Kvatinsky; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco; Sabina Spiga; Sergey Savelev; Alexander G. Balanov; Nitin Chawla; Giuseppe Desoli; et al. (CoRR, 2024)

Interplay Between Charge Defects and Ferroelectric Reliability: From Wake-Up, Imprint, Fatigue to Breakdown. - Chen-Yi Cho; Tzu-Yi Chao; Yu-Lin Shih; Tzu-Yao Lin; Tuo-Hung Hou (IRPS, 2025)