Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors. - Tuo Li 001; Roshan G. Ragel; Sri Parameswaran (DATE, 2012)

Fine-grained hardware/software methodology for process migration in MPSoCs. - Tuo Li 001; Jude Angelo Ambrose; Sri Parameswaran (ICCAD, 2012)

RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors. - Tuo Li 001; Muhammad Shafique 001; Jude Angelo Ambrose; Semeen Rehman; Jörg Henkel; Sri Parameswaran (DAC, 2013)

CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors. - Tuo Li 001; Muhammad Shafique 001; Semeen Rehman; Swarnalatha Radhakrishnan; Roshan G. Ragel; Jude Angelo Ambrose; Jörg Henkel; Sri Parameswaran (DATE, 2013)

DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems. - Tuo Li 001; Muhammad Shafique 001; Semeen Rehman; Jude Angelo Ambrose; Jörg Henkel; Sri Parameswaran (ICCAD, 2013)

Cost-Efficient Soft-Error Resiliency for ASIP-based Embedded Systems. - Tuo Li 001 (2013)

ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip. - Jude Angelo Ambrose; Nick Higgins; Mrinal Chakravarthy; Shivam Gargg; Tuo Li 001; Daniel Murphy; Aleksandar Ignjatovic; Sri Parameswaran (ISCAS, 2015)

Side channel attacks in embedded systems: A tale of hostilities and deterrence. - Jude Angelo Ambrose; Roshan G. Ragel; Darshana Jayasinghe; Tuo Li 001; Sri Parameswaran (ISQED, 2015)

ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA. - Jude Angelo Ambrose; Tuo Li 001; Daniel Murphy; Shivam Gargg; Nick Higgins; Sri Parameswaran (VLSID, 2015)

RECORD: Reducing register traffic for checkpointing in embedded processors. - Tuo Li 001; Jude Angelo Ambrose; Sri Parameswaran (DATE, 2016)

Processor Design for Soft Errors: Challenges and State of the Art. - Tuo Li 001; Jude Angelo Ambrose; Roshan G. Ragel; Sri Parameswaran (ACM Comput. Surv., 2016)

Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors. - Tuo Li 001; Muhammad Shafique 001; Jude Angelo Ambrose; Jörg Henkel; Sri Parameswaran (IEEE Trans. Computers, 2017)

A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic Units. - Hassaan Saadat; Tuo Li 001; Haris Javaid; Sri Parameswaran (VLSID, 2020)

SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation. - Tuo Li 001; Bradley Hopkins; Sri Parameswaran (CoRR, 2020)

Hardware Trojan Mitigation in Pipelined MPSoCs. - Amin Malekpour; Roshan G. Ragel; Tuo Li 001; Haris Javaid; Aleksandar Ignjatovic; Sri Parameswaran (ACM Trans. Design Autom. Electr. Syst., 2020)

SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V. - Hsu-Kang Dow; Tuo Li 001; William Miles; Sri Parameswaran (DAC, 2021)

COPS: A complete oblivious processing system. - Sajid Hussain; Hui Guo 001; Tuo Li 001; Hassaan Saadat; Sri Parameswaran (Microprocess. Microsystems, 2021)

FaSe: fast selective flushing to mitigate contention-based cache timing attacks. - Tuo Li 001; Sri Parameswaran (DAC, 2022)

HWST128: complete memory safety accelerator on RISC-V with metadata compression. - Hsu-Kang Dow; Tuo Li 001; Sri Parameswaran (DAC, 2022)

Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks. - Tuo Li 001; Sri Parameswaran (CoRR, 2022)

Accelerating Chaining in Genomic Analysis Using RISC- V Custom Instructions. - Kisaru Liyanage; Hasindu Gamaarachchi; Hassaan Saadat; Tuo Li 001; Hiruna Samarakoon; Sri Parameswaran (DATE, 2024)

MP-ORAM: A Novel ORAM Design for Multicore Processor Systems. - Sajid Hussain; Hui Guo 001; Tuo Li 001; Sri Parameswaran (IEEE Trans. Dependable Secur. Comput., 2024)