A ROM-less DDFS using a nonlinear DAC with an error compensation current array. - Chua-Chin Wang; Chia-Hao Hsu; Tuo-Yu Yao; Jian-Ming Huang (APCCAS, 2008)

Low-power 7.2 GHz Complementary All-N-Transistor Logic using 90 nm CMOS Technology. - Chia-Hao Hsu; Gang-Neng Sung; Tuo-Yu Yao; Chun-Ying Juan; Yain-Reu Lin; Chua-Chin Wang (ISCAS, 2009)