An optimized NoC architecture for accelerating TSP kernels in breakpoint median problem. - Turbo Majumder; Souradip Sarkar; Partha Pratim Pande; Ananth Kalyanaraman (ASAP, 2010)

Hardware accelerators for biocomputing: A survey. - Souradip Sarkar; Turbo Majumder; Ananth Kalyanaraman; Partha Pratim Pande (ISCAS, 2010)

Accelerating Maximum Likelihood Based Phylogenetic Kernels Using Network-on-Chip. - Turbo Majumder; Partha Pratim Pande; Ananth Kalyanaraman (SBAC-PAD, 2011)

NoC-Based Hardware Accelerator for Breakpoint Phylogeny. - Turbo Majumder; Souradip Sarkar; Partha Pratim Pande; Ananth Kalyanaraman (IEEE Trans. Computers, 2012)

On-Chip Network-Enabled Multicore Platforms Targeting Maximum Likelihood Phylogeny Reconstruction. - Turbo Majumder; Michael Edward Borgens; Partha Pratim Pande; Ananth Kalyanaraman (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Network-on-Chip with Long-Range Wireless Links for High-Throughput Scientific Computation. - Turbo Majumder; Partha Pratim Pande; Ananth Kalyanaraman (IPDPS Workshops, 2013)

High-throughput, energy-efficient network-on-chip-based hardware accelerators. - Turbo Majumder; Partha Pratim Pande; Ananth Kalyanaraman (Sustain. Comput. Informatics Syst., 2013)

Hardware Accelerators in Computational Biology: Application, Potential, and Challenges. - Turbo Majumder; Partha Pratim Pande; Ananth Kalyanaraman (IEEE Des. Test, 2014)

Wireless NoC Platforms With Dynamic Task Allocation for Maximum Likelihood Phylogeny Reconstruction. - Turbo Majumder; Partha Pratim Pande; Ananth Kalyanaraman (IEEE Des. Test, 2014)

NoC-enabled multicore architectures for stochastic analysis of biomolecular reactions. - Turbo Majumder; Xian Li; Paul Bogdan; Partha Pratim Pande (DATE, 2015)

On-chip network-enabled many-core architectures for computational biology applications. - Turbo Majumder; Partha Pratim Pande; Ananth Kalyanaraman (DATE, 2015)

Efficient Estimation of Non-stationary Traffic Parameters on Networks-on-Chip. - Abhishek Bansal; Sambhav Gupta; Turbo Majumder (IPDPS Workshops, 2015)

NoC router using STT-MRAM based hybrid buffers with error correction and limited flit retransmission. - Turbo Majumder; Manan Suri; Vinay Shekhar (ISCAS, 2015)

NoC Architectures as Enablers of Biological Discovery for Personalized and Precision Medicine. - Paul Bogdan; Turbo Majumder; Arvind Ramanathan; Yuankun Xue (NOCS, 2015)

An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS. - Somnath Paul; Vinayak Honkote; Ryan Gary Kim; Turbo Majumder; Paolo A. Aseron; Vaughn Grossnickle; Robert Sankman; Debendra Mallik; Sandeep Jain; Sriram R. Vangal; James W. Tschanz; Vivek De (VLSI Circuits, 2016)

Network-on-Chip-Enabled Multicore Platforms for Parallel Model Predictive Control. - Xian Li; Karthi Duraisamy; Paul Bogdan; Turbo Majumder; Partha Pratim Pande (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications. - Somnath Paul; Vinayak Honkote; Ryan Gary Kim; Turbo Majumder; Paolo A. Aseron; Vaughn Grossnickle; Robert Sankman; Debendra Mallik; Tao Wang; Sriram R. Vangal; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2017)

A Reconfigurable Wireless NoC for Large Scale Microbiome Community Analysis. - Xian Li; Karthi Duraisamy; Joe Baylon; Turbo Majumder; Guopeng Wei; Paul Bogdan; Deukhyoun Heo; Partha Pratim Pande (IEEE Trans. Computers, 2017)

2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads. - Charles Augustine; Somnath Paul; Turbo Majumder; James W. Tschanz; Muhammad M. Khellah; Vivek De (VLSI Circuits, 2020)

A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. - Somnath Paul; Turbo Majumder; Charles Augustine; Andres F. Malavasi; S. Usirikayala; Raghavan Kumar; Jisna Kollikunnel; S. Chhabra; Satish Yada; M. L. Barajas; Carlos Ornelas; Dan Lake; et al. (VLSI Circuits, 2020)