A 90 nm leakage control transistor based clock gating for low power flip flop applications. - Pritam Bhattacharjee; Alak Majumder; Tushar Dhabal Das (MWSCAS, 2016)

A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips. - Alak Majumder; Pritam Bhattacharjee; Tushar Dhabal Das (J. Circuits Syst. Comput., 2018)