A carbon nanotube transistor based RISC-V processor using pass transistor logic. - Aporva Amarnath; Siying Feng; Subhankar Pal; Tutu Ajayi; Austin Rovinski; Ronald G. Dreslinski (ISLPED, 2017)

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. - Scott Davidson 004; Shaolin Xie; Christopher Torng; Khalid Al-Hawaj; Austin Rovinski; Tutu Ajayi; Luis Vega; Chun Zhao; Ritchie Zhao; Steve Dai; Aporva Amarnath; Bandhav Veluri; et al. (IEEE Micro, 2018)

Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project. - Tutu Ajayi; Vidya A. Chhabria; Mateus Fogaça; Soheil Hashemi; Abdelrahman Hosny; Andrew B. Kahng; Minsoo Kim; Jeongsup Lee; Uday Mallappa; Marina Neseem; Geraldo Pradipta; Sherief Reda; et al. (DAC, 2019)

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. - Austin Rovinski; Chun Zhao; Khalid Al-Hawaj; Paul Gao 001; Shaolin Xie; Christopher Torng; Scott Davidson 004; Aporva Amarnath; Luis Vega; Bandhav Veluri; Anuj Rao; Tutu Ajayi; et al. (VLSI Circuits, 2019)

Bridging Academic Open-Source EDA to Real-World Usability. - Austin Rovinski; Tutu Ajayi; Minsoo Kim; Guanru Wang; Mehdi Saligane (ICCAD, 2020)

An Open-source Framework for Autonomous SoC Design with Analog Block Generation. - Tutu Ajayi; Sumanth Kamineni; Yaswanth K. Cherivirala; Morteza Fayazi; Kyumin Kwon; Mehdi Saligane; Shourya Gupta; Chien-Hen Chen; Dennis Sylvester; David T. Blaauw; Ronald G. Dreslinski; Benton H. Calhoun; et al. (VLSI-SOC, 2020)

Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation. - Tutu Ajayi; Sumanth Kamineni; Morteza Fayazi; Yaswanth K. Cherivirala; Kyumin Kwon; Shourya Gupta; Wenbo Duan; Jeongsup Lee; Chien-Hen Chen; Mehdi Saligane; Dennis Sylvester; David T. Blaauw; et al. (VLSI-SoC (Selected Papers), 2020)

Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm. - Sung Kim; Morteza Fayazi; Alhad Daftardar; Kuan-Yu Chen 001; Jielun Tan; Subhankar Pal; Tutu Ajayi; Yan Xiong 002; Trevor N. Mudge; Chaitali Chakrabarti; David T. Blaauw; Ronald G. Dreslinski; et al. (VLSI Circuits, 2021)

Enabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor. - Daniel W. Bliss; Tutu Ajayi; Ali Akoglu; Ilkin Aliyev; Toygun Basaklar; Leul Belayneh; David T. Blaauw; John S. Brunhaver; Chaitali Chakrabarti; Liangliang Chang; Kuan-Yu Chen 001; Ming-Hung Chen; et al. (ISCAS, 2022)

A Unified Forward Error Correction Accelerator for Multi-Mode Turbo, LDPC, and Polar Decoding. - Yufan Yue; Tutu Ajayi; Xueyang Liu; Peiwen Xing; Zihan Wang; David T. Blaauw; Ronald G. Dreslinski; Hun-Seok Kim (ISLPED, 2022)

Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory. - Sung Kim; Morteza Fayazi; Alhad Daftardar; Kuan-Yu Chen 001; Jielun Tan; Subhankar Pal; Tutu Ajayi; Yan Xiong 002; Trevor N. Mudge; Chaitali Chakrabarti; David T. Blaauw; Ronald G. Dreslinski; et al. (IEEE J. Solid State Circuits, 2022)

FASCINET: A Fully Automated Single-Board Computer Generator Using Neural Networks. - Morteza Fayazi; Zachary Colter; Zineb Benameur-El Youbi; Javad Bagherzadeh; Tutu Ajayi; Ronald G. Dreslinski (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

FALCON: An FPGA Emulation Platform for Domain-Specific SoCs (DSSoCs). - Anish Krishnakumar; Hanguang Yu; Tutu Ajayi; A. Alper Goksoy; Vishrut Pandey; Joshua Mack; Md Sahil Hassan; Kuan-Yu Chen 001; Chaitali Chakrabarti; Daniel W. Bliss; Ali Akoglu; Hun-Seok Kim; et al. (IEEE Des. Test, 2024)