Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. - Sandeep Kumar Goel; Saman Adham; Min-Jer Wang; Ji-Jan Chen; Tze-Chiang Huang; Ashok Mehta; Frank Lee 004; Vivek Chickermane; Brion L. Keller; Thomas Valind; Subhasish Mukherjee; Navdeep Sood; et al. (ITC, 2013)

A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application. - Mu-Shan Lin; Chien-Chun Tsai; Chih-Hsien Chang; Wen-Hung Huang; Ying-Yu Hsu; Shu-Chun Yang; Chin-Ming Fu; Mao-Hsuan Chou; Tien-Chien Huang; Ching-Fang Chen; Tze-Chiang Huang; Saman Adham; et al. (IEEE J. Solid State Circuits, 2014)

A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing. - Mu-Shan Lin; Tze-Chiang Huang; Chien-Chun Tsai; King-Ho Tam; Kenny Cheng-Hsiang Hsieh; Tom Chen 002; Wen-Hung Huang; Jack Hu; Yu-Chi Chen; Sandeep Kumar Goel; Chin-Ming Fu; Stefan Rusu; et al. (VLSI Circuits, 2019)

A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing. - Mu-Shan Lin; Tze-Chiang Huang; Chien-Chun Tsai; King-Ho Tam; Kenny Cheng-Hsiang Hsieh; Ching-Fang Chen; Wen-Hung Huang; Chi-Wei Hu; Yu-Chi Chen; Sandeep Kumar Goel; Chin-Ming Fu; Stefan Rusu; et al. (IEEE J. Solid State Circuits, 2020)

A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4. - Mu-Shan Lin; Chien-Chun Tsai; Shenggao Li; Tze-Chiang Huang; Wen-Hung Huang; Kate Huang; Yu-Chi Chen; Alex Liu; Yu-Jie Huang; Jimmy Wang; Shu-Chun Yang; Nai-Chen Cheng 001; et al. (VLSI Technology and Circuits, 2024)

An On-Chip Current-Sink-Free Adaptive-Timing Power Impedance Measurement (PIM) Unit for 3D-IC in 5nm FinFET Technology. - Tsung-Che Lu; Chin-Ming Fu; Wei-Hsiang Wang; Fred Kuo; Chih-Hsien Chang; Kenny Hsieh; King-Ho Tam; Tze-Chiang Huang; Tom Chen 002; Mei Wong; Wei-pin Changchien; Frank Lee 004 (VLSI Technology and Circuits, 2024)