An 8.5MHz 67.2dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90nm CMOS. - Chan-Hsiang Weng; Tzu-An Wei; Erkan Alpman; Chang-Tsung Fu; Yi-Ting Tseng; Tsung-Hsien Lin (VLSIC, 2014)

A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta-Sigma Modulator. - Chen-Chien Lin; Chan-Hsiang Weng; Tzu-An Wei; Yung-Yu Lin; Tsung-Hsien Lin (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 127 fJ/conv. continuous-time delta-sigma modulator with a DWA-embedded two-step time-domain quantizer. - Chan-Hsiang Weng; Tzu-An Wei; Tsung-Hsien Lin (VLSI-DAT, 2015)

A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer. - Chan-Hsiang Weng; Tzu-An Wei; Erkan Alpman; Chang-Tsung Fu; Tsung-Hsien Lin (IEEE J. Solid State Circuits, 2016)

A 71. 4dB SNDR 30MHz BW Continuous-Time Delta-sigma Modulator Using a Time-Interleaved Noise-Shaping Quantizer in 12-nm CMOS. - Chan-Hsiang Weng; Tzu-An Wei; Hung-Yi Hsieh; Su-Hao Wu; Ting-Yang Wang (VLSI Circuits, 2019)