Routability-driven analytical placement for mixed-size circuit designs. - Meng-Kai Hsu; Sheng Chou; Tzu-Hen Lin; Yao-Wen Chang (ICCAD, 2011)

Clock planning for multi-voltage and multi-mode designs. - Chang-Cheng Tsai; Tzu-Hen Lin; Shin-Han Tsai; Hung-Ming Chen (ISQED, 2011)

An efficient and effective analytical placer for FPGAs. - Tzu-Hen Lin; Pritha Banerjee 001; Yao-Wen Chang (DAC, 2013)

Design and manufacturing process co-optimization in nano-technology. - Meng-Kai Hsu; Nitesh Katta; Homer Yen-Hung Lin; Keny Tzu-Hen Lin; King Ho Tam; Ken Chung-Hsing Wang (ICCAD, 2014)

NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs. - Meng-Kai Hsu; Yi-Fang Chen; Chau-Chin Huang; Sheng Chou; Tzu-Hen Lin; Tung-Chieh Chen; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)