Symmetrical buffered clock-tree synthesis with supply-voltage alignment. - Xin-Wei Shih; Tzu-Hsuan Hsu; Hsu-Chieh Lee; Yao-Wen Chang; Kai-Yuan Chao (ASP-DAC, 2013)

Using condition flag prediction to improve the performance of out-of-order processors. - Tzu-Hsuan Hsu; Ching-Wen Lin; Chung-Ho Chen (ISCAS, 2013)

Buffered clock tree synthesis considering self-heating effects. - Chung-Wei Lin; Tzu-Hsuan Hsu; Xin-Wei Shih; Yao-Wen Chang (ISLPED, 2014)

Write-In-Place Operation and It's Advantages to Upgrade the 3D AND-type Flash Memory Performances. - Hang-Ting Lue; Tzu-Hsuan Hsu; Cheng-Lin Sung; Teng-Hao Yeh; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2021)

First Study of P-Channel Vertical Split-Gate Flash Memory Device with Various Electron and Hole Injection Methods and Potential Future Possibility to Enable Functional Memory Circuits. - Cheng-Lin Sung; Hang-Ting Lue; Wei-Chen Chen; Tzu-Hsuan Hsu; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2021)

Design of Computing-in-Memory (CIM) with Vertical Split-Gate Flash Memory for Deep Neural Network (DNN) Inference Accelerator. - Hang-Ting Lue; Han-Wen Hu; Tzu-Hsuan Hsu; Po-Kai Hsu; Keh-Chung Wang; Chih-Yuan Lu (ISCAS, 2021)

Using UTAUT, TTF, and PR integrating models to evaluate employees' acceptance and behavioral intention of PHM-based system in the military industry. - Tsung-Ti Chen; Yuan-Jen Chang; Tzu-Hsuan Hsu; He-Kai Hsu (ICPHM, 2022)

Graph Attention Transformer for Unsupervised Multivariate Time Series Anomaly Detection. - Tzu-Hsuan Hsu; Yu-Chee Tseng; Jen-Jee Chen (MACLEAN@PKDD/ECML, 2022)

A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device. - Wei-Chen Chen; Hang-Ting Lue; Tzu-Hsuan Hsu; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2023)