High-PSR bias circuitry for NTSC sync separation. - Chua-Chin Wang; Yih-Long Tseng; Tzung-Je Lee; Ron Hu (ISCAS (1), 2004)

A multiparameter implantable microstimulator SOC. - Chua-Chin Wang; Tzung-Je Lee; Yu-Tzu Hsiao; U. Fat Chio; Chi-Chun Huang; J.-J. J. Chin; Ya-Hsin Hsueh (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A Linear LDO Regulator with Modified NMCF Frequency Compensation Independent of Off-chip Capacitor and ESR. - Chua-Chin Wang; Chi-Chun Huang; Tzung-Je Lee; U. Fat Chio (APCCAS, 2006)

An Implantable SOC Chip for Micro-stimulating and Neural Signal Recording. - Chua-Chin Wang; Chi-Chun Huang; Tzung-Je Lee; Cheng-Mu Wu; Gang-Neng Sung; Kuan-Wen Fang; Sheng-Lun Tseng; Jia-Jin Chen (APCCAS, 2006)

An All-MOS High-Linearity Voltage-to-Frequency Converter Chip With 520-kHz/V Sensitivity. - Chua-Chin Wang; Tzung-Je Lee; Chih-Chen Li; Ron Hu (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

High-sensitivity and high-mobility compact DVB-T receiver for in-car entertainment. - Chua-Chin Wang; Tzung-Je Lee; Hoi Kam Lo; Shih-Ping Lin 002; Ron Hu (IEEE Trans. Consumer Electron., 2006)

Voltage-to-frequency converter with high sensitivity using all-MOS voltage window comparator. - Chua-Chin Wang; Tzung-Je Lee; Chih-Chen Li; Ron Hu (Microelectron. J., 2007)

Mixed-voltage I/O buffer using 0.35 μm CMOS technology. - Tzung-Je Lee; Wei-Chih Chang; Chua-Chin Wang (ICECS, 2008)

A 570-kbps ASK demodulator without external capacitors for low-frequency wireless bio-implants. - Chua-Chin Wang; Tzung-Je Lee; U. Fat Chio; Yu-Tzu Hsiao; Jia-Jin Chen (Microelectron. J., 2008)

All-MOS ASK Demodulator for Low-Frequency Applications. - Tzung-Je Lee; Ching-Li Lee; Yan-Jhin Ciou; Chi-Chun Huang; Chua-Chin Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators. - Tzung-Je Lee; Chua-Chin Wang (VLSI Design, 2008)

Wide-Range 5.0/3.3/1.8-V I/O Buffer Using 0.35-m 3.3-V CMOS Technology. - Tzung-Je Lee; Tieh-Yen Chang; Chua-Chin Wang (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

(1/3) times hboxVDD-to- (3/2) times hboxVDD Wide-Range I/O Buffer Using 0.35- muhboxm 3.3-V CMOS Technology. - Chi-Chun Huang; Tzung-Je Lee; Wei-Chih Chang; Chua-Chin Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Linear programmable gain amplifier using reconfiguration local-feedback transconductors. - Tzung-Je Lee; Wen-Je Lu; Wei-Chih Hsiao; Chua-Chin Wang (APCCAS, 2012)

Temperature and process compensated clock generator using feedback TPC bias. - Tzung-Je Lee; Doron Shmilovitz; Yi-Jie Hsieh; Chua-Chin Wang (ICICDT, 2012)

32% Slew rate and 27% data rate improved 2×VDD output buffer using PVTL compensation. - Tzung-Je Lee; Kai-Wei Ruan; Chua-Chin Wang (ICICDT, 2014)

9.9 V ASK Demodulator Using Differential Shaper for High-Impedance Electrode. - Tzung-Je Lee (Circuits Syst. Signal Process., 2014)

A ±3.07% frequency variation clock generator implemented using HV CMOS process. - Chua-Chin Wang; Deng-Shian Wang; Tzu-Chiao Sung; Yi-Jie Hsieh; Tzung-Je Lee (Microelectron. J., 2015)

16 Series Li-ion battery cells current sensor. - Tzung-Je Lee; Wun-Cing Yu; You-Ting Liu (ICCE-TW, 2016)

HV switch using differential voltage shaping driver for 13 series li-ion battery cells BMS. - Tzung-Je Lee (ISOCC, 2016)

PVT-independent dB-linear reconfigured local-feedback digital variable gain amplifier. - Tzung-Je Lee; Wei-Chih Hsiao (Microelectron. J., 2016)

HV voltage sensor for 16 series li-ion battery cells using chopper stabilized amplifier. - Tzung-Je Lee; Guan-Jhang Li (ISOCC, 2017)

A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer. - Tzung-Je Lee; Tsung-Yi Tsai; Wei Lin; U-Fat Chio; Chua-Chin Wang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Delay-Time-Compensated Peak Detector for Medium-Frequency Band. - Tzung-Je Lee; Wei-Chih Hsiao (Circuits Syst. Signal Process., 2018)

High Efficiency Buck Converter with Wide Load Current Range using Dual-Mode of PWM and PSM. - Tzung-Je Lee; Chia-Hsin Hsu; Chua-Chin Wang (ISCAS, 2019)

500 MHz 90 nm CMOS 2 ( times ) VDD Digital Output Buffer Immunity to Process and Voltage Variations. - Chua-Chin Wang; Tsung-Yi Tsai; Yu-Lin Deng; Tzung-Je Lee (Circuits Syst. Signal Process., 2019)

A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method. - Tzung-Je Lee; Tsung-Yi Tsai; Wei Lin; U. Fat Chio; Chua-Chin Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Slew Rate Enhanced 2 x VDD I/O Buffer With Precharge Timing Technique. - Tzung-Je Lee; Ssu-Wei Huang; Chua-Chin Wang (IEEE Trans. Circuits Syst., 2020)

A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment. - Tzung-Je Lee; Wen-Jian Su; Lean Karlo S. Tolentino; Chua-Chin Wang (APCCAS, 2021)

A 20 GHz 8-bit All-N-Transistor Logic CLA Using 16-nm FinFET Technology. - Tzung-Je Lee; Wen-Shou Yang; Chua-Chin Wang (APCCAS, 2021)

12 V PZE Harvesting Circuit For AUV Using Boost Converter with Resistor Matching Controller. - Tzung-Je Lee; Yu-Wei Liu (ISOCC, 2021)

2˟VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process. - Chua-Chin Wang; Pang-Yen Lou; Tsung-Yi Tsai; Yan-You Chou; Tzung-Je Lee (Circuits Syst. Signal Process., 2021)

High-Accuracy Impedance Read-out Circuit for BIA-type Biomedical Sensors. - Chua-Chin Wang; Pang-Yen Lou; Tsung-Yi Tsai; I-Yu Huang; Yu-Cheng Lin; Tzung-Je Lee; Guan-Ru Chen (Circuits Syst. Signal Process., 2021)

An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μm HV CMOS. - Chua-Chin Wang; Oliver Lexter July A. Jose; Po-Kai Su; Lean Karlo S. Tolentino; Ralph Gerard B. Sangalang; Jessica Velasco; Tzung-Je Lee (Microelectron. J., 2021)

Wide Lock-in Range CDR with Modified DQFD and Coarse-fine Tuning Technique. - Tzung-Je Lee; Bo-Hao Liao; Chua-Chin Wang (ICICDT, 2022)

Fast-Transient LDO Regulator with RC-less Low-Impedance Buffer and PVT Compensation. - Tzung-Je Lee; Hung-Hsiang Chang (ISOCC, 2022)

Wide Dynamic Range Temperature Sensor Using High Sensitivity PTAT Current Generator. - Tzung-Je Lee; Kuo-Hsun Tu (ISOCC, 2022)

A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process. - Jhih-Ying Ke; Lean Karlo S. Tolentino; Cheng-Yao Lo; Tzung-Je Lee; Chua-Chin Wang (APCCAS, 2023)

±3 A Bidirectional Current Sensor for 57.6 V Li-ion Battery Management System of AUV. - Tzung-Je Lee; Hsieng-Han Chen (ICCE-Taiwan, 2023)

Real-time IR Image Processing Interface on FPGA with Histogram Equalization and Non-Uniform Correction. - Tzung-Je Lee; Yu-Wei Liu; Yu-Cheng Lin (ICCE-Taiwan, 2023)

91.282% Efficiency SIDO Buck-Buck Converter with Separate Positive and Negative Output Voltage in 40 nm CMOS Process. - Tzung-Je Lee; Ding-Ze Chang (ISCAS, 2023)

3.2 Gbps Output Driver With Dual Low Voltage Modes and Low Power PVT Compensation Circuit. - Tzung-Je Lee; Shih-Hsien Kuo (ISCAS, 2023)

High Bandwidth Efficiency FPGA-based Underwater Acoustic Transceiver with Adaptive-SFDR DDFS. - Tzung-Je Lee; Hung-Hsiang Chang; Chien-Hsiang Chao (ISOCC, 2023)

Temperature Sensor with 292.3 nA/°C Sensitivity Using Double Current Subtraction. - Tzung-Je Lee; Yin-Wen Lo (ISOCC, 2023)

10-bit 250-KS/s M-2M Digital-to-Analog Converter with 4-4-2 Segmentation for Sonar System. - Tzung-Je Lee; Kuo-Hsun Tu (ISOCC, 2023)

A High Dynamic-Range Readout Circuit with Differential Resistance-to-Time Conversion for Gas Sensor. - Tzung-Je Lee; Meng-Lin Tsai (NEWCAS, 2023)

A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder. - Chua-Chin Wang; Oliver Lexter July A. Jose; Wen-Shou Yang; Ralph Gerard B. Sangalang; Lean Karlo S. Tolentino; Tzung-Je Lee (Circuits Syst. Signal Process., 2023)

A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process. - Chua-Chin Wang; Lean Karlo S. Tolentino; Shao-Wei Lu; Oliver Lexter July A. Jose; Ralph Gerard B. Sangalang; Tzung-Je Lee; Pang-Yen Lou; Wei-Chih Chang (Integr., 2023)

High-Sensitivity PTAT Current Generator Using PTAT and CTAT Current Subtraction Method for Temperature Sensor With Frequency Output. - Tzung-Je Lee; Kuo-Hsun Tu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process. - Jhih-Ying Ke; Lean Karlo Santos Tolentino; Cheng-Yao Lo; Tzung-Je Lee; Chua-Chin Wang (AICAS, 2024)

A High Gain Range Low Gain Step dB-Linear Programmable Gain Amplifier with Parallel Complementary Switching Current Method. - Tzung-Je Lee; Chien-Hsiang Chao (APCCAS, 2024)

A 23.9 ppm/°C Bandgap Reference Circuit with Wide Temperature Range Using Subthreshold PVT Detector. - Tzung-Je Lee; Ruei-Chi Lai; Aleksandr Vasjanov; Vaidotas Barzdenas (APCCAS, 2024)

A 3.2-GHz 0.3/0.5 V 16-nm FinFET I/O Buffer With Low-Power PVT Compensation Circuit. - Tzung-Je Lee; Ji-Hau Chiou (ISCAS, 2024)

A Cap-less LDO Regulator with Improved Load Regulation using Adaptive Feedback Control and Modified Voltage Damper. - Tzung-Je Lee; Han Yi Chiu (ISOCC, 2024)

Low-Power Frequency-Mode Temperature Sensing Circuit with Subthreshold Operational Amplifier. - Tzung-Je Lee; Po-Hsuan Hsiao (ISOCC, 2024)

Optimal Efficiency True Random Number Generator with Discrete-time Chaos for Low-Cost Applications. - Tzung-Je Lee; Cheng-Han Wu (ISOCC, 2024)

High efficiency active rectifier with low-power self-biased comparator for low-frequency piezoelectric vibration energy harvesting of AUV. - Tzung-Je Lee; Yu-Wei Liu (Microelectron. J., 2024)

A 1-6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD. - Chua-Chin Wang; L. S. S. Pavan Kumar Chodisetti; Bo-Hao Liao; Pradyumna Vellanki; Tzung-Je Lee (Microelectron. J., 2024)

A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm. - Chua-Chin Wang; L. S. S. Pavan Kumar Chodisetti; Jhih-Ying Ke; Cheng-Yao Lo; Tzung-Je Lee; Lean Karlo Santos Tolentino (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

98.9% Efficiency Fully-integrated GaN Driver for Underwater Wireless Charging Application. - Tzung-Je Lee; Yi-Ting Deng; Jyu-Heng Chen (ISCAS, 2025)