High Performance RDMA Based All-to-All Broadcast for InfiniBand Clusters. - Sayantan Sur; Uday Bondhugula; Amith R. Mamidala; Hyun-Wook Jin; Dhabaleswar K. Panda 001 (HiPC, 2005)

Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths. - Uday Bondhugula; Ananth Devulapalli; James Dinan; Joseph Fernando; Pete Wyckoff; Eric Stahlberg; P. Sadayappan (FCCM, 2006)

Parallel FPGA-based all-pairs shortest-paths in a directed graph. - Uday Bondhugula; Ananth Devulapalli; Joseph Fernando; Pete Wyckoff; P. Sadayappan (IPDPS, 2006)

Effective automatic parallelization of stencil computations. - Sriram Krishnamoorthy; Muthu Manikandan Baskaran; Uday Bondhugula; J. Ramanujam; Atanas Rountev; P. Sadayappan (PLDI, 2007)

Automatic mapping of nested loops to FPGAS. - Uday Bondhugula; J. Ramanujam; P. Sadayappan (PPoPP, 2007)

Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model. - Uday Bondhugula; Muthu Manikandan Baskaran; Sriram Krishnamoorthy; J. Ramanujam; Atanas Rountev; P. Sadayappan (CC, 2008)

A compiler framework for optimization of affine loop nests for gpgpus. - Muthu Manikandan Baskaran; Uday Bondhugula; Sriram Krishnamoorthy; J. Ramanujam; Atanas Rountev; P. Sadayappan (ICS, 2008)

Towards effective automatic parallelization for multicore systems. - Uday Bondhugula; Muthu Manikandan Baskaran; Albert Hartono; Sriram Krishnamoorthy; J. Ramanujam; Atanas Rountev; P. Sadayappan (IPDPS, 2008)

A practical automatic polyhedral parallelizer and locality optimizer. - Uday Bondhugula; Albert Hartono; J. Ramanujam; P. Sadayappan (PLDI, 2008)

Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories. - Muthu Manikandan Baskaran; Uday Bondhugula; Sriram Krishnamoorthy; J. Ramanujam; Atanas Rountev; P. Sadayappan (PPoPP, 2008)

Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors. - Qingda Lu; Christophe Alias; Uday Bondhugula; Thomas Henretty; Sriram Krishnamoorthy; J. Ramanujam; Atanas Rountev; P. Sadayappan; Yongjian Chen; Haibo Lin; Tin-Fook Ngai (PACT, 2009)

Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors. - Muthu Manikandan Baskaran; Nagavijayalakshmi Vydyanathan; Uday Bondhugula; J. Ramanujam; Atanas Rountev; P. Sadayappan (PPoPP, 2009)

Compact multi-dimensional kernel extraction for register tiling. - Lakshminarayanan Renganarayanan; Uday Bondhugula; Salem Derisavi; Alexandre E. Eichenberger; Kevin O'Brien (SC, 2009)

A model for fusion and code motion in an automatic parallelizing compiler. - Uday Bondhugula; Oktay Günlük; Sanjeeb Dash; Lakshminarayanan Renganarayanan (PACT, 2010)

Believe it or not!: mult-core CPUs can match GPU performance for a FLOP-intensive application! - Rajesh Bordawekar; Uday Bondhugula; Ravi Rao (PACT, 2010)

Combined Iterative and Model-driven Optimization in an Automatic Parallelization Framework. - Louis-Noël Pouchet; Uday Bondhugula; Cédric Bastoul; Albert Cohen 001; J. Ramanujam; P. Sadayappan (SC, 2010)

Loop transformations: convexity, pruning and optimization. - Louis-Noël Pouchet; Uday Bondhugula; Cédric Bastoul; Albert Cohen 001; J. Ramanujam; P. Sadayappan; Nicolas Vasilache (POPL, 2011)

Tiling stencil computations to maximize parallelism. - Vinayaka Bandishti; Irshad Pananilath; Uday Bondhugula (SC, 2012)

Generating efficient data movement code for heterogeneous architectures with distributed-memory. - Roshan Dathathri; Chandan Reddy 001; Thejas Ramashekar; Uday Bondhugula (PACT, 2013)

PolyGLoT: A Polyhedral Loop Transformation Framework for a Graphical Dataflow Language. - Somashekaracharya G. Bhaskaracharya; Uday Bondhugula (CC, 2013)

Compiling affine loop nests for distributed-memory parallel architectures. - Uday Bondhugula (SC, 2013)

Automatic data allocation and buffer management for multi-GPU machines. - Thejas Ramashekar; Uday Bondhugula (ACM Trans. Archit. Code Optim., 2013)

Tiling and optimizing time-iterated computations on periodic domains. - Uday Bondhugula; Vinayaka Bandishti; Albert Cohen 001; Guillain Potron; Nicolas Vasilache (PACT, 2014)

Effective automatic computation placement and dataallocation for parallelization of regular programs. - Chandan Reddy 001; Uday Bondhugula (ICS, 2014)

PolyMage: Automatic Optimization for Image Processing Pipelines. - Ravi Teja Mullapudi; Vinay Vasista; Uday Bondhugula (ASPLOS, 2015)

PLUTO+: near-complete modeling of affine transformations for parallelism and locality. - Aravind Acharya; Uday Bondhugula (PPoPP, 2015)

An Optimizing Code Generator for a Class of Lattice-Boltzmann Computations. - Irshad Pananilath; Aravind Acharya; Vinay Vasista; Uday Bondhugula (ACM Trans. Archit. Code Optim., 2015)

A DSL Compiler for Accelerating Image Processing Pipelines on FPGAs. - Nitin Chugh; Vinay Vasista; Suresh Purini; Uday Bondhugula (PACT, 2016)

SMO: an integrated approach to intra-array and inter-array storage optimization. - Somashekaracharya G. Bhaskaracharya; Uday Bondhugula; Albert Cohen 001 (POPL, 2016)

Compiling Affine Loop Nests for a Dynamic Scheduling Runtime on Shared and Distributed Memory. - Roshan Dathathri; Ravi Teja Mullapudi; Uday Bondhugula (ACM Trans. Parallel Comput., 2016)

Automatic Storage Optimization for Arrays. - Somashekaracharya G. Bhaskaracharya; Uday Bondhugula; Albert Cohen 001 (ACM Trans. Program. Lang. Syst., 2016)

The Pluto+ Algorithm: A Practical Approach for Parallelization and Locality Optimization of Affine Loop Nests. - Uday Bondhugula; Aravind Acharya; Albert Cohen 001 (ACM Trans. Program. Lang. Syst., 2016)

Optimizing geometric multigrid method computation using a DSL approach. - Vinay Vasista; Kumudha Narasimhan; Siddharth Bhat; Uday Bondhugula (SC, 2017)

Diamond Tiling: Tiling Techniques to Maximize Parallelism for Stencil Computations. - Uday Bondhugula; Vinayaka Bandishti; Irshad Pananilath (IEEE Trans. Parallel Distributed Syst., 2017)

Polyhedral auto-transformation with no integer linear programming. - Aravind Acharya; Uday Bondhugula; Albert Cohen 001 (PLDI, 2018)

An effective fusion and tile size model for optimizing image processing pipelines. - Abhinav Jangda; Uday Bondhugula (PPoPP, 2018)

Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths. - Vinamra Benara; Sahithi Rampalli; Ziaul Choudhury; Suresh Purini; Uday Bondhugula (CoRR, 2018)

An Approach for Finding Permutations Quickly: Fusion and Dimension matching. - Aravind Acharya; Uday Bondhugula; Albert Cohen 001 (CoRR, 2018)

Optimizing the linear fascicle evaluation algorithm for many-core systems. - Karan Aggarwal; Uday Bondhugula (ICS, 2019)

Optimizing the Linear Fascicle Evaluation Algorithm for Multi-Core and Many-Core Systems. - Karan Aggarwal; Uday Bondhugula; Varsha Sreenivasan; Devarajan Sridharan (CoRR, 2019)

A flexible FPGA accelerator for convolutional neural networks. - Kingshuk Majumder; Uday Bondhugula (CoRR, 2019)

Bitwidth customization in image processing pipelines using interval analysis and SMT solvers. - Suresh Purini; Vinamra Benara; Ziaul Choudhury; Uday Bondhugula (CC, 2020)

MLIR: A Compiler Infrastructure for the End of Moore's Law. - Chris Lattner; Jacques A. Pienaar; Mehdi Amini; Uday Bondhugula; River Riddle; Albert Cohen 001; Tatiana Shpeisman; Andy Davis; Nicolas Vasilache; Oleksandr Zinenko (CoRR, 2020)

High Performance Code Generation in MLIR: An Early Case Study with GEMM. - Uday Bondhugula (CoRR, 2020)

Effective Loop Fusion in Polyhedral Compilation Using Fusion Conflict Graphs. - Aravind Acharya; Uday Bondhugula; Albert Cohen 001 (ACM Trans. Archit. Code Optim., 2020)

Optimizing the Linear Fascicle Evaluation Algorithm for Multi-core and Many-core Systems. - Karan Aggarwal; Uday Bondhugula (ACM Trans. Parallel Comput., 2020)

An Effective Fusion and Tile Size Model for PolyMage. - Abhinav Jangda; Uday Bondhugula (ACM Trans. Program. Lang. Syst., 2020)

MLIR: Scaling Compiler Infrastructure for Domain Specific Computation. - Chris Lattner; Mehdi Amini; Uday Bondhugula; Albert Cohen 001; Andy Davis; Jacques A. Pienaar; River Riddle; Tatiana Shpeisman; Nicolas Vasilache; Oleksandr Zinenko (CGO, 2021)

A practical tile size selection model for affine loop nests. - Kumudha Narasimhan; Aravind Acharya; Abhinav Baid; Uday Bondhugula (ICS, 2021)

High Performance GPU Code Generation for Matrix-Matrix Multiplication using MLIR: Some Early Results. - Navdeep Katel; Vivek Khandelwal; Uday Bondhugula (CoRR, 2021)

MLIR-based code generation for GPU tensor cores. - Navdeep Katel; Vivek Khandelwal; Uday Bondhugula (CC, 2022)

Treebeard: An Optimizing Compiler for Decision Tree Based ML Inference. - Ashwin Prasad; Sampath Rajendra; Kaushik Rajan; R. Govindarajan; Uday Bondhugula (MICRO, 2022)

HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description. - Kingshuk Majumder; Uday Bondhugula (ASPLOS (4), 2023)

Automatic multi-dimensional pipelining for high-level synthesis of dataflow accelerators. - Kingshuk Majumder; Uday Bondhugula (CoRR, 2023)

SilvanForge: A Schedule-Guided Retargetable Compiler for Decision Tree Inference. - Ashwin Prasad; Sampath Rajendra; Kaushik Rajan; R. Govindarajan; Uday Bondhugula (SOSP, 2024)