Low-voltage linear OTA with rail-to-rail differential mode input signal capability. - X. W. Zhang; M. F. Li; Uday Dasgupta (ICECS, 1999)

Effects of resistive loading on unity gain frequency of two-stage CMOS operational amplifiers. - Uday Dasgupta; Yong Ping Xu (ISCAS (1), 2003)

High Power-supply Rejection Low Drop-out Regulator. - Uday Dasgupta; Alexander Tanzil (ISCAS, 2009)

An asynchronous sub-two-step quantizer for continuous-time sigma-delta modulators. - Xiao Liang Tan; Pak Kwong Chan; Uday Dasgupta (ISCAS, 2014)

A versatile three-stage operational amplifier with Second-stage Bypass Compensation. - Uday Dasgupta; Geok Teng Ong; Junmin Cao; Soong Lin Chew (ISIC, 2014)

9.1 A self-calibrating NFC SoC with a triple-mode reconfigurable PLL and a single-path PICC-PCD receiver in 0.11μm CMOS. - Wee Liang Lien; Tieng Yi Choke; Ying Chow Tan; Ming Kong; Eng-Chuan Low; Dan Ping Li; Liming Jin; Huajiang Zhang; Chin Heng Leow; Soong Lin Chew; Uday Dasgupta; Chee-Hong Yong; et al. (ISSCC, 2014)

A LDO Regulator With Weighted Current Feedback Technique for 0.47 nF-10 nF Capacitive Load. - Xiao Liang Tan; Sau Siong Chong; Pak Kwong Chan; Uday Dasgupta (IEEE J. Solid State Circuits, 2014)

A Sub-1-V 65-nm MOS Threshold Monitoring-Based Voltage Reference. - Xiao Liang Tan; Pak Kwong Chan; Uday Dasgupta (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Low voltage 2-stage and 3-stage push-pull output amplifiers in 65-nm CMOS technology. - Uday Dasgupta (ISIC, 2016)