Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design. - Bharat B. Sukhwani; Uday Padmanabhan; Janet Meiling Wang (DATE, 2005)

Statistical clock tree routing for robustness to process variations. - Uday Padmanabhan; Janet Meiling Wang; Jiang Hu (ISPD, 2006)

Simulation and Design of Nanocircuits With Resonant Tunneling Devices. - Janet Meiling Wang; Bharat Sukhwani; Uday Padmanabhan; Dongsheng Ma; Kartik Sinha (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Robust Clock Tree Routing in the Presence of Process Variations. - Uday Padmanabhan; Janet Meiling Wang; Jiang Hu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)