A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devices. - Oto Petura; Ugo Mureddu; Nathalie Bochard; Viktor Fischer; Lilian Bossuet (FPL, 2016)

Complete activation scheme for FPGA-oriented IP cores design protection. - Brice Colombier; Ugo Mureddu; Marek Laban; Oto Petura; Lilian Bossuet; Viktor Fischer (FPL, 2017)

A comprehensive hardware/software infrastructure for IP cores design protection. - Brice Colombier; Lilian Bossuet; Ugo Mureddu; David Hély (FPT, 2017)

Optimization of the PLL based TRNG design using the genetic algorithm. - Oto Petura; Ugo Mureddu; Nathalie Bochard; Viktor Fischer (ISCAS, 2017)

Efficient design of Oscillator based Physical Unclonable Functions on Flash FPGAs. - Ugo Mureddu; Oto Petura; Nathalie Bochard; Lilian Bossuet; Viktor Fischer (IVSW, 2017)

Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF. - Cédric Marchand 002; Lilian Bossuet; Ugo Mureddu; Nathalie Bochard; Abdelkarim Cherkaoui; Viktor Fischer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Transient Effect Ring Oscillators Leak Too. - Ugo Mureddu; Brice Colombier; Nathalie Bochard; Lilian Bossuet; Viktor Fischer (IACR Cryptol. ePrint Arch., 2019)

Experimental Study of Locking Phenomena on Oscillating Rings Implemented in Logic Devices. - Ugo Mureddu; Nathalie Bochard; Lilian Bossuet; Viktor Fischer (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

An Evaluation Procedure for Comparing Clock Jitter Measurement Methods. - Arturo Mollinedo Garay; Florent Bernard; Viktor Fischer; Patrick Haddad; Ugo Mureddu (CARDIS, 2022)