Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface. - Nam-Seog Kim; Yong-Jin Yoon; Uk-Rae Cho; Hyun-Geun Byun (CICC, 2003)

New dynamic logic-level converters for high performance application. - Nam-Seog Kim; Yong-Jin Yoon; Uk-Rae Cho; Hyun-Geun Byun (ISCAS (5), 2003)

A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM. - Uk-Rae Cho; Tae-Hyoung Kim; Yong-Jin Yoon; Jong-Cheol Lee; Dae-Gi Bae; Nam-Seog Kim; Kang-Young Kim; Young-Jae Son; Jeong-Suk Yang; Kwon-Il Sohn; Sung-Tae Kim; In-Yeol Lee; et al. (IEEE J. Solid State Circuits, 2003)

Modeling and Testing of Faults in TCAMs. - Kwang-Jin Lee; Cheol Kim; Suki Kim; Uk-Rae Cho; Hyun-Geun Byun (AsiaSim, 2004)

Synchronous mirror delay for multiphase locking. - Yong-Jin Yoon; Hyuck In Kwon; Jong Duk Lee; Byung Gook Park; Nam-Seog Kim; Uk-Rae Cho; Hyun-Geun Byun (IEEE J. Solid State Circuits, 2004)

Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application. - Nam-Seog Kim; Uk-Rae Cho; Hyun-Geun Byun (CICC, 2005)

A pseudo-differential CMOS receiver insensitive to input common mode level. - Nam-Seog Kim; Uk-Rae Cho; Hyun-Geun Byun (ISCAS (1), 2005)

A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch. - Tae-Hyoung Kim; Uk-Rae Cho; Hyun-Geun Byun (ISCAS (2), 2005)

A High Resolution, Wide Range Digital Impedance Controller. - Tae-Hyoung Kim; Kwang-Jin Lee; Uk-Rae Cho; Hyun-Geun Byun (IEICE Trans. Electron., 2005)

A Low Jitter ADPLL for Mobile Applications. - Kwang-Jin Lee; Hyo-Chang Kim; Uk-Rae Cho; Hyun-Geun Byun; Suki Kim (IEICE Trans. Electron., 2005)