Skew variation compensating technique for clock mesh networks. - Gunok Jung; Sahun Hong; Donggyu Lee; Jin-Soo Park; Sangdon Yi; Yohan Kwon; Ukrae Cho; Sung-Bae Park (APCCAS, 2008)

Fully digital clock frequency doubler. - Gunok Jung; Gi-Ho Park; Ukrae Cho; Jae-Cheol Son (IEICE Electron. Express, 2010)

A static-switching pulse domino technique for statistical power reduction of wide fan-in dynamic gates. - Rahul Singh; Jae-Cheol Son; Ukrae Cho; Gunok Jung; Min-Su Kim; Hyoungwook Lee; Suhwan Kim 001 (ACM Great Lakes Symposium on VLSI, 2011)

A 32nm high-k metal gate application processor with GHz multi-core CPU. - Se-Hyun Yang; Seogjun Lee; Jae Young Lee; Jeonglae Cho; Hoi-Jin Lee; Dongsik Cho; Junghun Heo; Sunghoon Cho; Youngmin Shin; Sunghee Yun; Euiseok Kim; Ukrae Cho; et al. (ISSCC, 2012)

Scan-controlled pulse flip-flops for mobile application processors. - Min-Su Kim; Hyoungwook Lee; Jin-Soo Park; Chunghee Kim; Juhyun Kang; Ken Shin; Emil Kagramanyan; Gunok Jung; Ukrae Cho; Youngmin Shin; Jae-Cheol Son (ISCAS, 2013)

28nm high- metal-gate heterogeneous quad-core CPUs for high-performance and energy-efficient mobile application processor. - Youngmin Shin; Ken Shin; Prashant Kenkare; Rajesh Kashyap; Hoi-Jin Lee; Dongjoo Seo; Brian Millar; Yohan Kwon; Ravi Iyengar; Min-Su Kim; Ahsan Chowdhury; Sung-il Bae; et al. (ISSCC, 2013)

23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor. - Jungyul Pyo; Youngmin Shin; Hoi-Jin Lee; Sung-il Bae; Min-Su Kim; Kwangil Kim; Ken Shin; Yohan Kwon; Heungchul Oh; Jaeyoung Lim; Dong-Wook Lee; Jongho Lee; et al. (ISSCC, 2015)