An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme. - Kyu-Hyoun Kim; Uksong Kang; Hoeju Chung; Dukha Park; Woo-Seop Kim; Young-Chan Jang; Moon-Sook Park; Hoon Lee; Jinyoung Kim; Jung Sunwoo; Hwan-Wook Park; Hyun-Kyung Kim; et al. (ISSCC, 2006)

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme. - Kyu-Hyoun Kim; Hoeju Chung; Woo-Seop Kim; Moon-Sook Park; Young-Chan Jang; Jinyoung Kim; Hwan-Wook Park; Uksong Kang; Paul W. Coteus; Joo-Sun Choi; Changhyun Kim (IEEE J. Solid State Circuits, 2007)

8Gb 3D DDR3 DRAM using through-silicon-via technology. - Uksong Kang; Hoeju Chung; Seongmoo Heo; Soon-Hong Ahn; Hoon Lee; Sooho Cha; Jaesung Ahn; Dukmin Kwon; Jin Ho Kim; Jae-Wook Lee 007; Han-Sung Joo; Woo-Seop Kim; et al. (ISSCC, 2009)

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology. - Uksong Kang; Hoeju Chung; Seongmoo Heo; Dukha Park; Hoon Lee; Jin Ho Kim; Soon-Hong Ahn; Sooho Cha; Jaesung Ahn; Dukmin Kwon; Jae-Wook Lee 007; Han-Sung Joo; et al. (IEEE J. Solid State Circuits, 2010)

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution. - Kyomin Sohn; Won-Joo Yun; Reum Oh; Chi-Sung Oh; Seong-Young Seo; Min-Sang Park; Dong-Hak Shin; Won-Chang Jung; Sang-Hoon Shin; Je-Min Ryu; Hye-Seung Yu; Jae-Hun Jung; et al. (ISSCC, 2016)

DRAMScale: Mechanisms to Increase DRAM Capacity. - Krishna T. Malladi; Uksong Kang; Manu Awasthi; Hongzhong Zheng (MEMSYS, 2016)

Dataplant: In-DRAM Security Mechanisms for Low-Cost Devices. - Lois Orosa 001; Yaohua Wang; Ivan Puddu; Mohammad Sadrosadati; Kaveh Razavi; Juan Gómez-Luna; Hasan Hassan; Nika Mansouri-Ghiasi; Arash Tavakkol; Minesh Patel; Jeremie S. Kim; Vivek Seshadri; et al. (CoRR, 2019)