Goal oriented slicing enumeration through shape function clipping. - Georg Sigl; Ulf Schlichtmann (EURO-DAC, 1991)

Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping. - Ulf Schlichtmann; Franc Brglez; Michael Hermann (DAC, 1992)

A new power estimation technique with application to decomposition of Boolean functions for low power. - Peter H. Schneider; Kurt Antreich; Ulf Schlichtmann (EURO-DAC, 1994)

Logiksynthese für komplexe anwenderprogrammierbare elektronische Bausteine. - Ulf Schlichtmann (1995)

Fast Power Estimation of Large Circuits. - Peter H. Schneider; Ulf Schlichtmann; Bernd Wurth (IEEE Des. Test Comput., 1996)

Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs. - Bernd Wurth; Ulf Schlichtmann; Klaus Eckl; Kurt Antreich (ACM Trans. Design Autom. Electr. Syst., 1999)

Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs. - K. Brock; C. Edwards; R. Lannoo; Ulf Schlichtmann; Antun Domic; Jacques Benkoski; David Overhauser; M. Kliment (DATE, 2002)

Systems Are Made from Transistors: UDSM Technology Creates New Challenges for Library and IC Development. - Ulf Schlichtmann (DSD, 2002)

Tomorrows High-Quality SoCs Require High-Quality Embedded Memories Today. - Ulf Schlichtmann (ISQED, 2002)

Ultra-Low-Power Design: Device and Logic Design Approaches. - Christoph Heer; Ulf Schlichtmann (Ultra Low-Power Electronics and Design, 2004)

Extremely Low-Power Logic. - Christian Piguet; Jacques Gautier; Christoph Heer; Ian O'Connor; Ulf Schlichtmann (DATE, 2004)

Design Methodology Innovations Address Manufacturing Technology Challenges: Power and Performance. - Ulf Schlichtmann (DSD, 2004)

Deterministic approaches to analog performance space exploration (PSE). - Daniel Mueller 001; Guido Stehr; Helmut E. Graeb; Ulf Schlichtmann (DAC, 2005)

Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen. - Daniel Mueller 001; Guido Stehr; Helmut E. Graeb; Ulf Schlichtmann (GI Jahrestagung (1), 2005)

A CPPLL hierarchical optimization methodology considering jitter, power and locking time. - Jun Zou; Daniel Mueller 001; Helmut E. Graeb; Ulf Schlichtmann (DAC, 2006)

DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design. - Markus Bühler; Jürgen Koehl; Jeanne Bickford; Jason Hibbeler; Ulf Schlichtmann; Ralf Sommer; Michael Pronath; Andreas Ripp (DATE, 2006)

Fast evaluation of analog circuit structures by polytopal approximations. - Daniel Mueller 001; Guido Stehr; Helmut E. Graeb; Ulf Schlichtmann (ISCAS, 2006)

Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts. - Jun Zou; Helmut Graeb; Daniel Mueller 001; Ulf Schlichtmann (CICC, 2007)

Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming. - Daniel Mueller 001; Helmut E. Graeb; Ulf Schlichtmann (DATE, 2007)

Pareto-Front Computation and Automatic Sizing of CPPLLs. - Jun Zou; Daniel Mueller 001; Helmut E. Graeb; Ulf Schlichtmann (ISQED, 2007)

Sizing Rules for Bipolar Analog Circuit Design. - Tobias Massier; Helmut E. Graeb; Ulf Schlichtmann (DATE, 2008)

Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions. - Martin Strasser; Michael Eick; Helmut Gräb; Ulf Schlichtmann; Frank M. Johannes (ICCAD, 2008)

A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters. - Michael Pehl; Tobias Massier; Helmut E. Graeb; Ulf Schlichtmann (ICCD, 2008)

Abacus: fast legalization of standard cell circuits with minimal movement. - Peter Spindler; Ulf Schlichtmann; Frank M. Johannes (ISPD, 2008)

Static Timing Model Extraction for Combinational Circuits. - Bing Li 005; Christoph Knoth; Walter Schneider 001; Manuel Schmidt; Ulf Schlichtmann (PATMOS, 2008)

A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA. - Walter Schneider 001; Manuel Schmidt; Bing Li 005; Ulf Schlichtmann (PATMOS, 2008)

The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis. - Tobias Massier; Helmut E. Graeb; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Kraftwerk2 - A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model. - Peter Spindler; Ulf Schlichtmann; Frank M. Johannes (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Fast and waveform independent characterization of current source models. - Christoph Knoth; Veit B. Kleeberger; Petra Nordholz; Ulf Schlichtmann (BMAS, 2009)

On hierarchical statistical static timing analysis. - Bing Li 005; Ning Chen 006; Manuel Schmidt; Walter Schneider 001; Ulf Schlichtmann (DATE, 2009)

Digital design at a crossroads How to make statistical design methodologies industrially relevant. - Ulf Schlichtmann; Manuel Schmidt; Harald Kinzelbach; Michael Pronath; Volker Glöckel; Manfred Dietrich; Uwe Eichler; Joachim Haase (DATE, 2009)

A free-shape router for analog and RF applications. - Engin Avci; Martin Strasser; Helmut Graeb; Ulf Schlichtmann (ECCTD, 2009)

Timing model extraction for sequential circuits considering process variations. - Bing Li 005; Ning Chen 006; Ulf Schlichtmann (ICCAD, 2009)

Sensitivity based parameter reduction for statistical analysis of circuit performance. - Ning Chen 006; Bing Li 005; Ulf Schlichtmann (ICECS, 2009)

Aging analysis of circuit timing considering NBTI and HCI. - Dominik Lorenz; Georg Georgakos; Ulf Schlichtmann (IOLTS, 2009)

On-Chip Electric Waves: An Analog Circuit Approach to Physical Uncloneable Functions. - György Csaba; Xueming Ju; Qingqing Chen 004; Wolfgang Porod; Jürgen Schmidhuber; Ulf Schlichtmann; Paolo Lugli; Ulrich Rührmair (IACR Cryptol. ePrint Arch., 2009)

Towards Electrical, Integrated Implementations of SIMPL Systems. - Ulrich Rührmair; Qingqing Chen 004; Paolo Lugli; Ulf Schlichtmann; Martin Stutzmann; György Csaba (IACR Cryptol. ePrint Arch., 2009)

Pareto optimization of analog circuits considering variability. - Helmut Graeb; Daniel Mueller-Gritschneder; Ulf Schlichtmann (Int. J. Circuit Theory Appl., 2009)

A Successive Approach to Compute the Bounded Pareto Front of Practical Multiobjective Optimization Problems. - Daniel Mueller-Gritschneder; Helmut E. Graeb; Ulf Schlichtmann (SIAM J. Optim., 2009)

Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods. - Bing Li 005; Ning Chen 006; Ulf Schlichtmann (ICCAD, 2010)

Aging analysis at gate and macro cell level. - Dominik Lorenz; Martin Barke; Ulf Schlichtmann (ICCAD, 2010)

Automatic generation of hierarchical placement rules for analog integrated circuits. - Michael Eick; Martin Strasser; Helmut E. Graeb; Ulf Schlichtmann (ISPD, 2010)

White-Box Current Source Modeling Including Parameter Variation and Its Application in Timing Simulation. - Christoph Knoth; Irina Eichwald; Petra Nordholz; Ulf Schlichtmann (PATMOS, 2010)

Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level (Alterungsanalyse von kombinatorischen Schaltungen auf Gatterebene). - Dominik Lorenz; Georg Georgakos; Ulf Schlichtmann (it Inf. Technol., 2010)

Design and architectures for dependable embedded systems. - Jörg Henkel; Lars Bauer; Joachim Becker; Oliver Bringmann 001; Uwe Brinkschulte; Samarjit Chakraborty; Michael Engel; Rolf Ernst; Hermann Härtig; Lars Hedrich; Andreas Herkersdorf; Rüdiger Kapitza; et al. (CODES+ISSS, 2011)

Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level. - Daniel Mueller-Gritschneder; Kun Lu 005; Ulf Schlichtmann (DSD, 2011)

The Bistable Ring PUF: A new architecture for strong Physical Unclonable Functions. - Qingqing Chen 004; György Csaba; Paolo Lugli; Ulf Schlichtmann; Ulrich Rührmair (HOST, 2011)

Timing Modeling of Flipflops Considering Aging Effects. - Ning Chen 006; Bing Li 005; Ulf Schlichtmann (PATMOS, 2011)

Iterative Timing Analysis Considering Interdependency of Setup and Hold Times. - Ning Chen 006; Bing Li 005; Ulf Schlichtmann (PATMOS, 2011)

SWAT: Simulator for Waveform-Accurate Timing Including Parameter Variations and Transistor Aging. - Christoph Knoth; Carsten Uphoff; Sebastian Kiesel; Ulf Schlichtmann (PATMOS, 2011)

Removal of unnecessary context switches from the systemc simulation kernel for fast VP simulation. - Kun Lu 005; Daniel Mueller-Gritschneder; Ulf Schlichtmann (ICSAMOS, 2011)

Circuit-Based Approaches to Simpl Systems. - Qingqing Chen 004; György Csaba; Paolo Lugli; Ulf Schlichtmann; Martin Stutzmann; Ulrich Rührmair (J. Circuits Syst. Comput., 2011)

Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits. - Michael Eick; Martin Strasser; Kun Lu 005; Ulf Schlichtmann; Helmut E. Graeb (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs. - Vladimir Todorov; Alberto Ghiribaldi; Helmut Reinig; Davide Bertozzi; Ulf Schlichtmann (CODES+ISSS, 2012)

Characterization of the bistable ring PUF. - Qingqing Chen 004; György Csaba; Paolo Lugli; Ulf Schlichtmann; Ulrich Rührmair (DATE, 2012)

Current source modeling for power and timing analysis at different supply voltages. - Christoph Knoth; Hela Jedda; Ulf Schlichtmann (DATE, 2012)

Accurately timed transaction level models for virtual prototyping at high abstraction level. - Kun Lu 005; Daniel Mueller-Gritschneder; Ulf Schlichtmann (DATE, 2012)

Automated construction of a cycle-approximate transaction level model of a memory controller. - Vladimir Todorov; Daniel Mueller-Gritschneder; Helmut Reinig; Ulf Schlichtmann (DATE, 2012)

Hierarchical control flow matching for source-level simulation of embedded software. - Kun Lu 005; Daniel Müller-Gritschneder; Ulf Schlichtmann (ISSoC, 2012)

Schedulability Analysis for Processors with Aging-Aware Autonomic Frequency Scaling. - Alejandro Masrur; Philipp H. Kindt; Martin Becker 001; Samarjit Chakraborty; Veit Kleeberger; Martin Barke; Ulf Schlichtmann (RTCSA, 2012)

Iterative timing analysis based on nonlinear and interdependent flipflop modelling. - Ning Chen 006; Bing Li 005; Ulf Schlichtmann (IET Circuits Devices Syst., 2012)

ICMAT 2011 - Reliability and variability of semiconductor devices and ICs. - Asen Asenov; Ulf Schlichtmann; Cher Ming Tan; Hei Wong; Xing Zhou (Microelectron. Reliab., 2012)

Efficiently analyzing the impact of aging effects on large integrated circuits. - Dominik Lorenz; Martin Barke; Ulf Schlichtmann (Microelectron. Reliab., 2012)

Statistical Timing Analysis for Latch-Controlled Circuits With Reduced Iterations and Graph Transformations. - Bing Li 005; Ning Chen 006; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Memory access reconstruction based on memory allocation mechanism for source-level simulation of embedded software. - Kun Lu 005; Daniel Mueller-Gritschneder; Ulf Schlichtmann (ASP-DAC, 2013)

Reliability challenges for electric vehicles: from devices to architecture and systems software. - Georg Georgakos; Ulf Schlichtmann; Reinhard Schneider 001; Samarjit Chakraborty (DAC, 2013)

Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies. - Veit Kleeberger; Helmut E. Graeb; Ulf Schlichtmann (DAC, 2013)

Fast cache simulation for host-compiled simulation of embedded software. - Kun Lu 005; Daniel Mueller-Gritschneder; Ulf Schlichtmann (DATE, 2013)

Analytical timing estimation for temporally decoupled TLMs considering resource conflicts. - Kun Lu 005; Daniel Mueller-Gritschneder; Ulf Schlichtmann (DATE, 2013)

A virtual prototyping platform for real-time systems with a case study for a two-wheeled robot. - Daniel Mueller-Gritschneder; Kun Lu 005; Erik Wallander; Marc Greim; Ulf Schlichtmann (DATE, 2013)

A spectral clustering approach to application-specific network-on-chip synthesis. - Vladimir Todorov; Daniel Mueller-Gritschneder; Helmut Reinig; Ulf Schlichtmann (DATE, 2013)

Technology-aware system failure analysis in the presence of soft errors by Mixture Importance Sampling. - Veit Kleeberger; Daniel Mueller-Gritschneder; Ulf Schlichtmann (DFTS, 2013)

Post-route refinement for high-frequency PCBs considering meander segment alleviation. - Tsun-Ming Tseng; Bing Li 005; Tsung-Yi Ho; Ulf Schlichtmann (ACM Great Lakes Symposium on VLSI, 2013)

PROTON: an automatic place-and-route tool for optical networks-on-chip. - Anja Boos; Luca Ramini; Ulf Schlichtmann; Davide Bertozzi (ICCAD, 2013)

Post-route alleviation of dense meander segments in high-performance printed circuit boards. - Tsun-Ming Tseng; Bing Li 005; Tsung-Yi Ho; Ulf Schlichtmann (ICCAD, 2013)

A greedy approach for latency-bounded deadlock-free routing path allocation for application-specific NoCs. - Amit Verma; Pritpal S. Multani; Daniel Mueller-Gritschneder; Vladimir Todorov; Ulf Schlichtmann (NOCS, 2013)

Application of Dempster-Shafer Theory to task mapping under epistemic uncertainty. - Carsten Uphoff; Daniel Mueller-Gritschneder; Ulf Schlichtmann (SysCon, 2013)

A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience. - Veit Kleeberger; Christina Gimmler-Dumont; Christian Weis; Andreas Herkersdorf; Daniel Mueller-Gritschneder; Sani R. Nassif; Ulf Schlichtmann; Norbert Wehn (IEEE Micro, 2013)

On Timing Model Extraction and Hierarchical Statistical Timing Analysis. - Bing Li 005; Ning Chen 006; Yang Xu 019; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Workload- and Instruction-Aware Timing Analysis: The missing Link between Technology and System-level Resilience. - Veit Kleeberger; Petra R. Maier; Ulf Schlichtmann (DAC, 2014)

Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges. - Jan-Hendrik Oetjens; Nico Bannow; Markus Becker 001; Oliver Bringmann 001; Andreas Burger; Moomen Chaari; Samarjit Chakraborty; Rolf Drechsler; Wolfgang Ecker; Kim Grüttner; Thomas Kruse; Christoph Kuznik; et al. (DAC, 2014)

Probabilistic standard cell modeling considering non-Gaussian parameters and correlations. - André Lange; Christoph Sohrmann; Roland Jancke; Joachim Haase; Ingolf Lorenz; Ulf Schlichtmann (DATE, 2014)

Special session: How secure are PUFs really? On the reach and limits of recent PUF attacks. - Ulrich Rührmair; Ulf Schlichtmann; Wayne P. Burleson (DATE, 2014)

Connecting different worlds - Technology abstraction for reliability-aware design and Test. - Ulf Schlichtmann; Veit Kleeberger; Jacob A. Abraham; Adrian Evans; Christina Gimmler-Dumont; Michael Glaß; Andreas Herkersdorf; Sani R. Nassif; Norbert Wehn (DATE, 2014)

Fault-tolerant embedded control systems for unreliable hardware. - Dip Goswami; Daniel Mueller-Gritschneder; Twan Basten; Ulf Schlichtmann; Samarjit Chakraborty (ISIC, 2014)

System C-based multi-level error injection for the evaluation of fault-tolerant systems. - Daniel Mueller-Gritschneder; Petra R. Maier; Marc Greim; Ulf Schlichtmann (ISIC, 2014)

Emulated ASIC Power and Temperature Monitor System for FPGA Prototyping of an Invasive MPSoC Computing Architecture. - Elisabeth Glocker; Qingqing Chen 004; Asheque M. Zaidi; Ulf Schlichtmann; Doris Schmitt-Landsiedel (CoRR, 2014)

An Analysis of Industrial SRAM Test Results - A Comprehensive Study on Effectiveness and Classification of March Test Algorithms. - Michael Linder; Alfred Eder; Ulf Schlichtmann; Klaus Oberländer (IEEE Des. Test, 2014)

Special section reliability and variability of devices for circuits and systems. - Asen Asenov; Ulf Schlichtmann; Cher Ming Tan; Hei Wong; Xing Zhou (Microelectron. Reliab., 2014)

Robustness measurement of integrated circuits and its adaptation to aging effects. - Martin Barke; Michael Kärgel; Markus Olbrich; Ulf Schlichtmann (Microelectron. Reliab., 2014)

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience. - Andreas Herkersdorf; Hananeh Aliee; Michael Engel; Michael Glaß; Christina Gimmler-Dumont; Jörg Henkel; Veit Kleeberger; Michael A. Kochte; Johannes Maximilian Kühn; Daniel Mueller-Gritschneder; Sani R. Nassif; Holm Rauchfuss; et al. (Microelectron. Reliab., 2014)

A compact model for NBTI degradation and recovery under use-profile variations and its application to aging analysis of digital integrated circuits. - Veit B. Kleeberger; Martin Barke; Christoph Werner; Doris Schmitt-Landsiedel; Ulf Schlichtmann (Microelectron. Reliab., 2014)

Monitoring of aging in integrated circuits by identifying possible critical paths. - Dominik Lorenz; Martin Barke; Ulf Schlichtmann (Microelectron. Reliab., 2014)

Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies. - Vladimir Todorov; Daniel Mueller-Gritschneder; Helmut Reinig; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

GRIP: grammar-based IP integration and packaging for acceleration-rich SoC designs. - Munish Jassi; Daniel Müller-Gritschneder; Ulf Schlichtmann (DAC, 2015)

Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mapping. - Tsun-Ming Tseng; Bing Li 005; Tsung-Yi Ho; Ulf Schlichtmann (DAC, 2015)

Timing verification for adaptive integrated circuits. - Rohit Kumar 001; Bing Li 005; Yiren Shen; Ulf Schlichtmann; Jiang Hu (DATE, 2015)

Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip. - Yong Hu; Daniel Müller-Gritschneder; Martha Johanna Sepúlveda; Guy Gogniat; Ulf Schlichtmann (INA-OCMC@HiPEAC, 2015)

Beyond GORDIAN and Kraftwerk: EDA Research at TUM. - Ulf Schlichtmann (ISPD, 2015)

Emulation of an ASIC power and temperature monitor system for FPGA prototyping. - Elisabeth Glocker; Qingqing Chen 004; Asheque M. Zaidi; Ulf Schlichtmann; Doris Schmitt-Landsiedel (ReCoSoC, 2015)

Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays. - Éricles Sousa; Frank Hannig; Jürgen Teich; Qingqing Chen 004; Ulf Schlichtmann (SCOPES, 2015)

MWA Skew SRAM Based SIMPL Systems for Public-Key Physical Cryptography. - Qingqing Chen 004; Ulrich Rührmair; Spoorthy Narayana; Uzair Sharif; Ulf Schlichtmann (TRUST, 2015)

Integrating aging aware timing analysis into a commercial STA tool. - Shushanik Karapetyan; Ulf Schlichtmann (VLSI-DAT, 2015)

Storage and Caching: Synthesis of Flow-Based Microfluidic Biochips. - Tsun-Ming Tseng; Bing Li 005; Ulf Schlichtmann; Tsung-Yi Ho (IEEE Des. Test, 2015)

Application-aware cross-layer reliability analysis and optimization. - Michael Glaß; Hananeh Aliee; Liang Chen 014; Mojtaba Ebrahimi; Faramarz Khosravi; Veit B. Kleeberger; Alexandra Listl; Daniel Müller-Gritschneder; Fabian Oboril; Ulf Schlichtmann; Mehdi Baradaran Tahoori; Jürgen Teich; et al. (it Inf. Technol., 2015)

A Cross-Layer Approach to Measure the Robustness of Integrated Circuits. - Martin Barke; Ulf Schlichtmann (ACM J. Emerg. Technol. Comput. Syst., 2015)

Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements. - Bing Li 005; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing. - Tsun-Ming Tseng; Bing Li 005; Tsung-Yi Ho; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits. - Ulf Schlichtmann; Masanori Hashimoto; Iris Hui-Ru Jiang; Bing Li 005 (ASP-DAC, 2016)

Fault injection at host-compiled level with static fault set reduction for SoC firmware robustness testing. - Petra R. Maier; Veit Kleeberger; Daniel Mueller-Gritschneder; Ulf Schlichtmann (CODES+ISSS, 2016)

Columba: co-layout synthesis for continuous-flow microfluidic biochips. - Tsun-Ming Tseng; Mengchu Li; Bing Li 005; Tsung-Yi Ho; Ulf Schlichtmann (DAC, 2016)

Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing. - Tsun-Ming Tseng; Bing Li 005; Ching-Feng Yeh; Hsiang-Chieh Jhan; Zuo-Min Tsai; Mark Po-Hung Lin; Ulf Schlichtmann (DAC, 2016)

EffiTest: efficient delay test and statistical prediction for configuring post-silicon tunable buffers. - Grace Li Zhang; Bing Li 005; Ulf Schlichtmann (DAC, 2016)

Sieve-valve-aware synthesis of flow-based microfluidic biochips considering specific biological execution limitations. - Mengchu Li; Tsun-Ming Tseng; Bing Li 005; Tsung-Yi Ho; Ulf Schlichtmann (DATE, 2016)

Sampling-based buffer insertion for post-silicon yield improvement under process variability. - Grace Li Zhang; Bing Li 005; Ulf Schlichtmann (DATE, 2016)

Fully synthesized time-to-digital converter for cellular transceivers. - Dimo Martev; Sven Hampel; Ulf Schlichtmann (EBCCSP, 2016)

Hardware-Accelerated Software Library Drivers Generation for IP-Centric SoC Designs. - Munish Jassi; Uzair Sharif; Daniel Müller-Gritschneder; Ulf Schlichtmann (ACM Great Lakes Symposium on VLSI, 2016)

Where formal verification can help in functional safety analysis. - Alessandro Bernardini; Wolfgang Ecker; Ulf Schlichtmann (ICCAD, 2016)

Control-fluidic CoDesign for paper-based digital microfluidic biochips. - Qin Wang 005; Zeyan Li; Haena Cheong; Oh-Sun Kwon; Hailong Yao; Tsung-Yi Ho; Kwanwoo Shin; Bing Li 005; Ulf Schlichtmann; Yici Cai (ICCAD, 2016)

From biochips to quantum circuits: computer-aided design for emerging technologies. - Robert Wille; Bing Li 005; Ulf Schlichtmann; Rolf Drechsler (ICCAD, 2016)

PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency using a piecewise model. - Grace Li Zhang; Bing Li 005; Ulf Schlichtmann (ICCAD, 2016)

Safety evaluation based on virtual prototypes: Fault injection with multi-level processor models. - Daniel Mueller-Gritschneder; Marc Greim; Ulf Schlichtmann (ISIC, 2016)

PLATON: A Force-Directed Placement Algorithm for 3D Optical Networks-on-Chip. - Anja von Beuningen; Ulf Schlichtmann (ISPD, 2016)

Synthesis-based methodology for high-speed multi-modulus divider. - Dimo Martev; Sven Hampel; Ulf Schlichtmann (SMACD, 2016)

On the measurement of power grid robustness under load uncertainties. - Jie Wu 023; Ulf Schlichtmann; Yiyu Shi 001 (SmartGridComm, 2016)

Efficient handling of the fault space in functional safety analysis utilizing formal methods. - Alessandro Bernardini; Wolfgang Ecker; Ulf Schlichtmann (VLSI-SoC, 2016)

Dark silicon management: an integrated and coordinated cross-layer approach. - Santiago Pagani; Lars Bauer; Qingqing Chen 004; Elisabeth Glocker; Frank Hannig; Andreas Herkersdorf; Heba Khdr; Anuj Pathania; Ulf Schlichtmann; Doris Schmitt-Landsiedel; Mark Sagi; Éricles Sousa; et al. (it Inf. Technol., 2016)

PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer. - Anja von Beuningen; Luca Ramini; Davide Bertozzi; Ulf Schlichtmann (ACM J. Emerg. Technol. Comput. Syst., 2016)

Editorial. - Asen Asenov; Ulf Schlichtmann; Cher Ming Tan; Hei Wong; Xing Zhou (Microelectron. Reliab., 2016)

FinFET-based product performance: Modeling and evaluation of standard cells in FinFET technologies. - Shushanik Karapetyan; Veit Kleeberger; Ulf Schlichtmann (Microelectron. Reliab., 2016)

Multivariate Modeling of Variability Supporting Non-Gaussian and Correlated Parameters. - André Lange; Christoph Sohrmann; Roland Jancke; Joachim Haase; Binjie Cheng; Asen Asenov; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Reliability-Aware Synthesis With Dynamic Device Mapping and Fluid Routing for Flow-Based Microfluidic Biochips. - Tsun-Ming Tseng; Bing Li 005; Mengchu Li; Tsung-Yi Ho; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips. - Qin Wang 005; Shiliang Zuo; Hailong Yao; Tsung-Yi Ho; Bing Li 005; Ulf Schlichtmann; Yici Cai (ASP-DAC, 2017)

Component-Oriented High-level Synthesis for Continuous-Flow Microfluidics Considering Hybrid-Scheduling. - Mengchu Li; Tsun-Ming Tseng; Bing Li 005; Tsung-Yi Ho; Ulf Schlichtmann (DAC, 2017)

Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage. - Chunfeng Liu; Bing Li 005; Hailong Yao; Paul Pop; Tsung-Yi Ho; Ulf Schlichtmann (DAC, 2017)

CoSyn: Efficient single-cell analysis using a hybrid microfluidic platform. - Mohamed Ibrahim 002; Krishnendu Chakrabarty; Ulf Schlichtmann (DATE, 2017)

Testing microfluidic Fully Programmable Valve Arrays (FPVAs). - Chunfeng Liu; Bing Li 005; Bhargab B. Bhattacharya; Krishnendu Chakrabarty; Tsung-Yi Ho; Ulf Schlichtmann (DATE, 2017)

Reliability-aware synthesis and fault test of fully programmable valve arrays (FPVAs). - Bing Li 005; Ulf Schlichtmann (DFT, 2017)

A Method for Phase Noise Analysis of RF Circuits. - Dimo Martev; Sven Hampel; Ulf Schlichtmann (ACM Great Lakes Symposium on VLSI, 2017)

Model-based framework for networks-on-chip design space exploration. - Yong Hu; Daniel Müller-Gritschneder; Ulf Schlichtmann (AISTECS@HiPEAC, 2017)

Sortex: Efficient timing-driven synthesis of reconfigurable flow-based biochips for scalable single-cell screening. - Mohamed Ibrahim 002; Aditya Sridhar; Krishnendu Chakrabarty; Ulf Schlichtmann (ICCAD, 2017)

Methodology for automated phase noise minimization in RF circuit interconnect trees. - Dimo Martev; Sven Hampel; Ulf Schlichtmann (ISCAS, 2017)

The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping. - Daniel Mueller-Gritschneder; Keerthikumara Devarajegowda; Martin Dittrich; Wolfgang Ecker; Marc Greim; Ulf Schlichtmann (RSP, 2017)

Frontiers of timing. - Ulf Schlichtmann (SLIP, 2017)

20nm FinFET-based SRAM cell: Impact of variability and design choices on performance characteristics. - Shushanik Karapetyan; Ulf Schlichtmann (SMACD, 2017)

Generative adversarial network based scalable on-chip noise sensor placement. - Jinglan Liu; Yukun Ding; Jianlei Yang 001; Ulf Schlichtmann; Yiyu Shi 001 (SoCC, 2017)

Application of machine learning methods in post-silicon yield improvement. - Baris Yigit; Grace Li Zhang; Bing Li 005; Yiyu Shi 001; Ulf Schlichtmann (SoCC, 2017)

Fast Statistical Timing Analysis for Circuits with Post-Silicon Tunable Clock Buffers. - Bing Li 005; Ning Chen 006; Ulf Schlichtmann (CoRR, 2017)

Emulation of an ASIC power and temperature monitoring system (eTPMon) for FPGA prototyping. - Elisabeth Glocker; Qingqing Chen 004; Ulf Schlichtmann; Doris Schmitt-Landsiedel (Microprocess. Microsystems, 2017)

Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips. - Qin Wang 005; Yue Xu; Shiliang Zuo; Hailong Yao; Tsung-Yi Ho; Bing Li 005; Ulf Schlichtmann; Yici Cai (IEEE Trans. Biomed. Circuits Syst., 2017)

An Efficient Two-Phase ILP-Based Algorithm for Precise CMOS RFIC Layout Generation. - Tsun-Ming Tseng; Bing Li 005; Ching-Feng Yeh; Hsiang-Chieh Jhan; Zuo-Min Tsai; Mark Po-Hung Lin; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

On enabling diagnosis for 1-Pin Test fails in an industrial flow. - Daniel Tille; Benedikt Gottinger; Ulrike Pfannkuchen; Helmut Graeb; Ulf Schlichtmann (ASP-DAC, 2018)

PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chip. - Yu-Kai Chuang; Kuan-Jung Chen; Kun-Lin Lin; Shao-Yun Fang; Bing Li 005; Ulf Schlichtmann (DAC, 2018)

Design-for-testability for continuous-flow microfluidic biochips. - Chunfeng Liu; Bing Li 005; Tsung-Yi Ho; Krishnendu Chakrabarty; Ulf Schlichtmann (DAC, 2018)

Columba S: a scalable co-layout design automation tool for microfluidic large-scale integration. - Tsun-Ming Tseng; Mengchu Li; Daniel Nestor Freitas; Amy Mongersun; Ismail Emre Araci; Tsung-Yi Ho; Ulf Schlichtmann (DAC, 2018)

Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units. - Grace Li Zhang; Bing Li 005; Masanori Hashimoto; Ulf Schlichtmann (DAC, 2018)

Fault-tolerant valve-based microfluidic routing fabric for droplet barcoding in single-cell analysis. - Yasamin Moradi; Mohamed Ibrahim 002; Krishnendu Chakrabarty; Ulf Schlichtmann (DATE, 2018)

ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques. - Daniel Mueller-Gritschneder; Martin Dittrich; Josef Weinzierl; Eric Cheng; Subhasish Mitra; Ulf Schlichtmann (DATE, 2018)

TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing. - Grace Li Zhang; Bing Li 005; Bei Yu 001; David Z. Pan; Ulf Schlichtmann (DATE, 2018)

An efficient fault-tolerant valve-based microfluidic routing fabric for single-cell analysis. - Yasamin Moradi; Krishnendu Chakrabarty; Ulf Schlichtmann (ETS, 2018)

Automated Redirection of Hardware Accesses for Host-Compiled Software Simulation. - Rafael Stahl; Daniel Mueller-Gritschneder; Ulf Schlichtmann (FDL, 2018)

Automatic Design of Microfluidic Devices. - Robert Wille; Bing Li 005; Rolf Drechsler; Ulf Schlichtmann (FDL, 2018)

Wavefront-MCTS: multi-objective design space exploration of NoC architectures based on Monte Carlo tree search. - Yong Hu; Daniel Mueller-Gritschneder; Ulf Schlichtmann (ICCAD, 2018)

CustomTopo: a topology generation method for application-specific wavelength-routed optical NoCs. - Mengchu Li; Tsun-Ming Tseng; Davide Bertozzi; Mahdi Tala; Ulf Schlichtmann (ICCAD, 2018)

Performance and accuracy in soft-error resilience evaluation using the multi-level processor simulator ETISS-ML. - Daniel Mueller-Gritschneder; Uzair Sharif; Ulf Schlichtmann (ICCAD, 2018)

Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips. - Ying Zhu 008; Bing Li 005; Tsung-Yi Ho; Qin Wang 005; Hailong Yao; Robert Wille; Ulf Schlichtmann (ICCAD, 2018)

Test generation for microfluidic fully programmable valve arrays (FPVAs) with heuristic acceleration. - Chunfeng Liu; Bing Li 005; Bhargab B. Bhattacharya; Krishnendu Chakrabarty; Tsung-Yi Ho; Ulf Schlichtmann (ICICDT, 2018)

Emulation of an ASIC Power, Temperature and Aging Monitor System for FPGA Prototyping. - Alexandra Listl; Daniel Mueller-Gritschneder; Fabian Kluge; Ulf Schlichtmann (IOLTS, 2018)

Efficient Fault Injection for Embedded Systems: As Fast as Possible but as Accurate as Necessary. - Petra R. Maier; Uzair Sharif; Daniel Mueller-Gritschneder; Ulf Schlichtmann (IOLTS, 2018)

Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips. - Fengxian Jiao; Sheqin Dong; Bei Yu 001; Bing Li 005; Ulf Schlichtmann (ISCAS, 2018)

Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security. - Grace Li Zhang; Bing Li 005; Ulf Schlichtmann (ISVLSI, 2018)

From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era. - Bing Li 005; Masanori Hashimoto; Ulf Schlichtmann (IPSJ Trans. Syst. LSI Des. Methodol., 2018)

Efficient spanning-tree-based test pattern generation for Programmable Microfluidic Devices. - Alessandro Bernardini; Chunfeng Liu; Bing Li 005; Ulf Schlichtmann (Microelectron. J., 2018)

Columba 2.0: A Co-Layout Synthesis Tool for Continuous-Flow Microfluidic Biochips. - Tsun-Ming Tseng; Mengchu Li; Daniel Nestor Freitas; Travis McAuley; Bing Li 005; Tsung-Yi Ho; Ismail Emre Araci; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning. - Grace Li Zhang; Bing Li 005; Jinglan Liu; Yiyu Shi 001; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Fault Injection for Test-Driven Development of Robust SoC Firmware. - Petra R. Maier; Veit B. Kleeberger; Daniel Mueller-Gritschneder; Ulf Schlichtmann (ACM Trans. Embed. Comput. Syst., 2018)

Graph-Grammar-Based IP-Integration (GRIP) - An EDA Tool for Software-Defined SoCs. - Munish Jassi; Yong Hu; Daniel Mueller-Gritschneder; Ulf Schlichtmann (ACM Trans. Design Autom. Electr. Syst., 2018)

Automated Phase-Noise-Aware Design of RF Clock Distribution Circuits. - Dimo Martev; Sven Hampel; Ulf Schlichtmann (IEEE Trans. Very Large Scale Integr. Syst., 2018)

SeRoHAL: generation of selectively robust hardware abstraction layers for efficient protection of mixed-criticality systems. - Petra R. Kleeberger; Juana Rivera; Daniel Mueller-Gritschneder; Ulf Schlichtmann (ASP-DAC, 2019)

Cross-Layer Resilience: Challenges, Insights, and the Road Ahead. - Eric Cheng; Daniel Mueller-Gritschneder; Jacob A. Abraham; Pradip Bose; Alper Buyuktosunoglu; Deming Chen; Hyungmin Cho; Yanjing Li; Uzair Sharif; Kevin Skadron; Mircea Stan; Ulf Schlichtmann; et al. (DAC, 2019)

MiniControl: Synthesis of Continuous-Flow Microfluidics with Strictly Constrained Control Ports. - Xing Huang 001; Tsung-Yi Ho; Wenzhong Guo; Bing Li 005; Ulf Schlichtmann (DAC, 2019)

ACCESS: HW/SW Co-Equivalence Checking for Firmware Optimization. - Michael Schwarz 010; Raphael Stahl; Daniel Müller-Gritschneder; Ulf Schlichtmann; Dominik Stoffel; Wolfgang Kunz (DAC, 2019)

Fault Localization in Programmable Microfluidic Devices. - Alessandro Bernardini; Chunfeng Liu; Bing Li 005; Ulf Schlichtmann (DATE, 2019)

Physical Synthesis of Flow-Based Microfluidic Biochips Considering Distributed Channel Storage. - Zhisheng Chen 002; Xing Huang 001; Wenzhong Guo; Bing Li 005; Tsung-Yi Ho; Ulf Schlichtmann (DATE, 2019)

Towards Reliable and Secure Post-Quantum Co-Processors based on RISC-V. - Tim Fritzmann; Uzair Sharif; Daniel Müller-Gritschneder; Cezar Reinbrecht; Ulf Schlichtmann; Johanna Sepúlveda (DATE, 2019)

Block-Flushing: A Block-based Washing Algorithm for Programmable Microfluidic Devices. - Yu-Huei Lin; Tsung-Yi Ho; Bing Li 005; Ulf Schlichtmann (DATE, 2019)

SRAM Design Exploration with Integrated Application-Aware Aging Analysis. - Alexandra Listl; Daniel Mueller-Gritschneder; Ulf Schlichtmann; Sani R. Nassif (DATE, 2019)

Aging-aware Lifetime Enhancement for Memristor-based Neuromorphic Computing. - Shuhang Zhang; Grace Li Zhang; Bing Li 005; Hai Helen Li; Ulf Schlichtmann (DATE, 2019)

VOM: Flow-Path Validation and Control-Sequence Optimization for Multilayered Continuous-Flow Microfluidic Biochips. - Mengchu Li; Tsun-Ming Tseng; Yanlu Ma; Tsung-Yi Ho; Ulf Schlichtmann (ICCAD, 2019)

Overview of 2019 CAD Contest at ICCAD. - Ulf Schlichtmann; Sabya Das; Ing-Chao Lin; Mark Po-Hung Lin (ICCAD, 2019)

Cloud Columba: Accessible Design Automation Platform for Production and Inspiration: Invited Paper. - Tsun-Ming Tseng; Mengchu Li; Yushen Zhang; Tsung-Yi Ho; Ulf Schlichtmann (ICCAD, 2019)

Wavelength-Routed Optical NoCs: Design and EDA - State of the Art and Future Directions: Invited Paper. - Tsun-Ming Tseng; Alexandre Truppel; Mengchu Li; Mahdi Nikdast; Ulf Schlichtmann (ICCAD, 2019)

A Compact Model of Negative Bias Temperature Instability Suitable for Gate-Level Circuit Simulation. - Xu Liu; Alessandro Bernardini; Ulf Schlichtmann; Xing Zhou (ISQED, 2019)

MAGIC: A Wear-leveling Circuitry to Mitigate Aging Effects in Sense Amplifiers of SRAMs. - Alexandra Listl; Daniel Mueller-Gritschneder; Ulf Schlichtmann (NEWCAS, 2019)

Fully Distributed Deep Learning Inference on Resource-Constrained Edge Devices. - Rafael Stahl; Zhuoran Zhao 001; Daniel Mueller-Gritschneder; Andreas Gerstlauer; Ulf Schlichtmann (SAMOS, 2019)

Emerging Hardware Techniques and EDA Methodologies for Neuromorphic Computing (Dagstuhl Seminar 19152). - Krishnendu Chakrabarty; Tsung-Yi Ho; Hai Li 001; Ulf Schlichtmann (Dagstuhl Reports, 2019)

Synthesis of a Cyberphysical Hybrid Microfluidic Platform for Single-Cell Analysis. - Mohamed Ibrahim 002; Krishnendu Chakrabarty; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Synthesis of Reconfigurable Flow-Based Biochips for Scalable Single-Cell Screening. - Mohamed Ibrahim 002; Aditya Sridhar; Krishnendu Chakrabarty; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations. - Grace Li Zhang; Bing Li 005; Yiyu Shi 001; Jiang Hu; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Lifetime Enhancement for RRAM-based Computing-In-Memory Engine Considering Aging and Thermal Effects. - Shuhang Zhang; Grace Li Zhang; Bing Li 005; Hai Helen Li; Ulf Schlichtmann (AICAS, 2020)

Maximizing the Communication Parallelism for Wavelength-Routed Optical Networks-On-Chips. - Mengchu Li; Tsun-Ming Tseng; Mahdi Tala; Ulf Schlichtmann (ASP-DAC, 2020)

Investigating the Inherent Soft Error Resilience of Embedded Applications by Full-System Simulation. - Uzair Sharif; Daniel Mueller-Gritschneder; Ulf Schlichtmann (ASP-DAC, 2020)

Timing Resilience for Efficient and Secure Circuits. - Grace Li Zhang; Michaela Brunner; Bing Li 005; Georg Sigl; Ulf Schlichtmann (ASP-DAC, 2020)

Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays. - Gautam Choudhary; Sandeep Pal; Debraj Kundu; Sukanta Bhattacharjee; Shigeru Yamashita; Bing Li 005; Ulf Schlichtmann; Sudip Roy 001 (DATE, 2020)

A Pulse-width Modulation Neuron with Continuous Activation for Processing-In-Memory Engines. - Shuhang Zhang; Bing Li 005; Hai Helen Li; Ulf Schlichtmann (DATE, 2020)

Statistical Training for Neuromorphic Computing using Memristor-based Crossbars Considering Process Variations and Noise. - Ying Zhu 008; Grace Li Zhang; Tianchen Wang; Bing Li 005; Yiyu Shi 001; Tsung-Yi Ho; Ulf Schlichtmann (DATE, 2020)

Reliable and Robust RRAM-based Neuromorphic Computing. - Grace Li Zhang; Bing Li 005; Ying Zhu 008; Shuhang Zhang; Tianchen Wang; Yiyu Shi 001; Tsung-Yi Ho; Hai (Helen) Li; Ulf Schlichtmann (ACM Great Lakes Symposium on VLSI, 2020)

PathDriver: A Path-Driven Architectural Synthesis Flow for Continuous-Flow Microfluidic Biochips. - Xing Huang 001; Youlin Pan; Grace Li Zhang; Bing Li 005; Wenzhong Guo; Tsung-Yi Ho; Ulf Schlichtmann (ICCAD, 2020)

Overview of 2020 CAD Contest at ICCAD. - Ing-Chao Lin; Ulf Schlichtmann; Tsung-Wei Huang; Mark Po-Hung Lin (ICCAD, 2020)

PSION 2: Optimizing Physical Layout of Wavelength-Routed ONoCs for Laser Power Reduction. - Alexandre Truppel; Tsun-Ming Tseng; Ulf Schlichtmann (ICCAD, 2020)

Countering Variations and Thermal Effects for Accurate Optical Neural Networks. - Ying Zhu 008; Grace Li Zhang; Bing Li 005; Xunzhao Yin; Cheng Zhuo; Huaxi Gu; Tsung-Yi Ho; Ulf Schlichtmann (ICCAD, 2020)

Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors. - Riccardo Cantoro; Martin Huch; Tobias Kilian; Raffaele Martone; Ulf Schlichtmann; Giovanni Squillero (ITC, 2020)

Partial Sharing Neural Networks for Multi-Target Regression on Power and Performance of Embedded Memories. - Felix Last; Ulf Schlichtmann (MLCAD, 2020)

Runtime Monitoring of Inter- and Intra-Thread Requirements on Embedded MPSoCs. - Marcel Mettler; Daniel Mueller-Gritschneder; Ulf Schlichtmann (VLSID, 2020)

TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix). - Grace Li Zhang; Bing Li 005; Meng Li 004; Bei Yu 001; David Z. Pan; Michaela Brunner; Georg Sigl; Ulf Schlichtmann (CoRR, 2020)

Driver Generation for IoT Nodes With Optimization of the Hardware/Software Interface. - Rafael Stahl; Daniel Mueller-Gritschneder; Ulf Schlichtmann (IEEE Embed. Syst. Lett., 2020)

Machine learning and structural characteristics for reverse engineering. - Johanna Baehr 001; Alessandro Bernardini; Georg Sigl; Ulf Schlichtmann (Integr., 2020)

Test Generation for Flow-Based Microfluidic Biochips With General Architectures. - Chunfeng Liu; Bing Li 005; Bhargab B. Bhattacharya; Krishnendu Chakrabarty; Tsung-Yi Ho; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

An Efficient Fault-Tolerant Valve-Based Microfluidic Routing Fabric for Droplet Barcoding in Single-Cell Analysis. - Yasamin Moradi; Mohamed Ibrahim 002; Krishnendu Chakrabarty; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

PSION+: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs. - Alexandre Truppel; Tsun-Ming Tseng; Davide Bertozzi; José Carlos Alves; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips. - Qin Wang 005; Ulf Schlichtmann; Yici Cai; Weiqing Ji; Zeyan Li; Haena Cheong; Oh-Sun Kwon; Hailong Yao; Tsung-Yi Ho; Kwanwoo Shin; Bing Li 005 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing. - Grace Li Zhang; Bing Li 005; Meng Li 004; Bei Yu 001; David Z. Pan; Michaela Brunner; Georg Sigl; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic Biochips. - Ying Zhu 008; Xing Huang 001; Bing Li 005; Tsung-Yi Ho; Qin Wang 005; Hailong Yao; Robert Wille; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs. - Yong Hu; Marcel Mettler; Daniel Mueller-Gritschneder; Thomas Wild; Andreas Herkersdorf; Ulf Schlichtmann (ACM Trans. Design Autom. Electr. Syst., 2020)

Predicting Memory Compiler Performance Outputs Using Feed-forward Neural Networks. - Felix Last; Max Haeberlein; Ulf Schlichtmann (ACM Trans. Design Autom. Electr. Syst., 2020)

Connection-based Processing-In-Memory Engine Design Based on Resistive Crossbars. - Shuhang Zhang; Hai Helen Li; Ulf Schlichtmann (ASP-DAC, 2021)

Robustness of Neuromorphic Computing with RRAM-based Crossbars and Optical Neural Networks. - Grace Li Zhang; Bing Li 005; Ying Zhu 008; Tianchen Wang; Yiyu Shi 001; Xunzhao Yin; Cheng Zhuo; Huaxi Gu; Tsung-Yi Ho; Ulf Schlichtmann (ASP-DAC, 2021)

Light: A Scalable and Efficient Wavelength-Routed Optical Networks-On-Chip Topology. - Zhidan Zheng; Mengchu Li; Tsun-Ming Tseng; Ulf Schlichtmann (ASP-DAC, 2021)

Bayesian Inference Based Robust Computing on Memristor Crossbar. - Di Gao; Qingrong Huang; Grace Li Zhang; Xunzhao Yin; Bing Li 005; Ulf Schlichtmann; Cheng Zhuo (DAC, 2021)

FAST: A Fast Automatic Sweeping Topology Customization Method for Application-Specific Wavelength-Routed Optical NoCs. - Xiao Moyuan; Tsun-Ming Tseng; Ulf Schlichtmann (DATE, 2021)

Energy-Aware Designs of Ferroelectric Ternary Content Addressable Memory. - Yu Qian; Zhenhao Fan; Haoran Wang; Chao Li 065; Mohsen Imani; Kai Ni 004; Grace Li Zhang; Bing Li 005; Ulf Schlichtmann; Cheng Zhuo; Xunzhao Yin (DATE, 2021)

Hardware-Software Codesign of Weight Reshaping and Systolic Array Multiplexing for Efficient CNNs. - Jingyao Zhang 002; Huaxi Gu; Grace Li Zhang; Bing Li 005; Ulf Schlichtmann (DATE, 2021)

An Efficient Programming Framework for Memristor-based Neuromorphic Computing. - Grace Li Zhang; Bing Li 005; Xing Huang 001; Chen Shen; Shuhang Zhang; Florin Burcea; Helmut Graeb; Tsung-Yi Ho; Hai Li 001; Ulf Schlichtmann (DATE, 2021)

Exploiting Active Learning for Microcontroller Performance Prediction. - Nicolò Bellarmino; Riccardo Cantoro; Martin Huch; Tobias Kilian; Raffaele Martone; Ulf Schlichtmann; Giovanni Squillero (ETS, 2021)

Reliable Memristor-based Neuromorphic Design Using Variation- and Defect-Aware Training. - Di Gao; Grace Li Zhang; Xunzhao Yin; Bing Li 005; Ulf Schlichtmann; Cheng Zhuo (ICCAD, 2021)

BigIntegr: One-Pass Architectural Synthesis for Continuous-Flow Microfluidic Lab-on-a-Chip Systems. - Xing Huang 001; Youlin Pan; Zhen Chen; Wenzhong Guo; Robert Wille; Tsung-Yi Ho; Ulf Schlichtmann (ICCAD, 2021)

Manufacturing Cycle-Time Optimization Using Gaussian Drying Model for Inkjet-Printed Electronics. - Tsun-Ming Tseng; Meng Lian 001; Mengchu Li; Philipp Rinklin; Leroy Grob; Bernhard Wolfrum; Ulf Schlichtmann (ICCAD, 2021)

Peripheral Circuitry Assisted Mapping Framework for Resistive Logic-In-Memory Computing. - Shuhang Zhang; Hai Li 001; Ulf Schlichtmann (ICCAD, 2021)

ToPro: A Topology Projector and Waveguide Router for Wavelength-Routed Optical Networks-on-Chip. - Zhidan Zheng; Mengchu Li; Tsun-Ming Tseng; Ulf Schlichtmann (ICCAD, 2021)

Relative-Scheduling-Based High-Level Synthesis for Flow-Based Microfluidic Biochips. - Fangda Zuo; Mengchu Li; Tsun-Ming Tseng; Tsung-Yi Ho; Ulf Schlichtmann (ICCAD, 2021)

RobustONoC: Fault-Tolerant Optical Networks-on-Chip with Path Backup and Signal Reflection. - Yu-Kai Chuang; Yong Zhong; Yi-Hao Cheng; Bo-Yi Yu; Shao-Yun Fang; Bing Li 005; Ulf Schlichtmann (ISQED, 2021)

A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators. - Tobias Kilian; Heiko Ahrens; Daniel Tille; Martin Huch; Ulf Schlichtmann (ITC, 2021)

Feeding Hungry Models Less: Deep Transfer Learning for Embedded Memory PPA Models : Special Session. - Felix Last; Ulf Schlichtmann (MLCAD, 2021)

Learning based Memory Interference Prediction for Co-running Applications on Multi-Cores. - Ahsan Saeed; Daniel Mueller-Gritschneder; Falk Rehm; Arne Hamann 001; Dirk Ziegenbein; Ulf Schlichtmann; Andreas Gerstlauer (MLCAD, 2021)

Report on First and Second ACM/IEEE Workshop on Machine Learning for CAD (MLCAD). - Marilyn Wolf; Jörg Henkel; Raviv Gal; Ulf Schlichtmann (IEEE Des. Test, 2021)

DeeperThings: Fully Distributed CNN Inference on Resource-Constrained Edge Devices. - Rafael Stahl; Alexander Hoffman; Daniel Mueller-Gritschneder; Andreas Gerstlauer; Ulf Schlichtmann (Int. J. Parallel Program., 2021)

A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs. - Marcel Mettler; Daniel Mueller-Gritschneder; Ulf Schlichtmann (ACM Trans. Archit. Code Optim., 2021)

DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips. - Chunfeng Liu; Xing Huang 001; Bing Li 005; Hailong Yao; Paul Pop; Tsung-Yi Ho; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

REPAIR: Control Flow Protection based on Register Pairing Updates for SW-Implemented HW Fault Tolerance. - Uzair Sharif; Daniel Mueller-Gritschneder; Ulf Schlichtmann (ACM Trans. Embed. Comput. Syst., 2021)

Differentially Evolving Memory Ensembles: Pareto Optimization based on Computational Intelligence for Embedded Memories on a System Level. - Felix Last; Ceren Yeni; Ulf Schlichtmann (ASP-DAC, 2022)

Energy efficient data search design and optimization based on a compact ferroelectric FET content addressable memory. - Jiahao Cai; Mohsen Imani; Kai Ni 004; Grace Li Zhang; Bing Li 005; Ulf Schlichtmann; Cheng Zhuo; Xunzhao Yin (DAC, 2022)

GNN-based concentration prediction for random microfluidic mixers. - Weiqing Ji; Xingzhuo Guo; Shouan Pan; Tsung-Yi Ho; Ulf Schlichtmann; Hailong Yao (DAC, 2022)

Contamination-Free Switch Design and Synthesis for Microfluidic Large-Scale Integration. - Duan Shen; Yushen Zhang; Mengchu Li; Tsun-Ming Tseng; Ulf Schlichtmann (DATE, 2022)

RRAM-based Neuromorphic Computing: Data Representation, Architecture, Logic, and Programming. - Grace Li Zhang; Shuhang Zhang; Hai Helen Li; Ulf Schlichtmann (DSD, 2022)

Test, Reliability and Functional Safety Trends for Automotive System-on-Chip. - Francesco Angione; Davide Appello; J. Aribido; Jyotika Athavale; Nicolò Bellarmino; Paolo Bernardi; Riccardo Cantoro; Corrado De Sio; Tommaso Foscale; Gabriele Gavarini; J. Guerrero; Martin Huch; et al. (ETS, 2022)

Reducing Routing Overhead by Self-Enabling Functional Path Ring Oscillators. - Tobias Kilian; Markus Hanel; Daniel Tille; Martin Huch; Ulf Schlichtmann (ETS, 2022)

CorePerfDSL: A Flexible Processor Description Language for Software Performance Simulation. - Conrad Foik; Daniel Mueller-Gritschneder; Ulf Schlichtmann (FDL, 2022)

CoMUX: Combinatorial-Coding-Based High-Performance Microfluidic Control Multiplexer Design. - Siyuan Liang; Mengchu Li; Tsun-Ming Tseng; Ulf Schlichtmann; Tsung-Yi Ho (ICCAD, 2022)

Microcontroller Performance Screening: Optimizing the Characterization in the Presence of Anomalous and Noisy Data. - Nicolò Bellarmino; Riccardo Cantoro; Martin Huch; Tobias Kilian; Ulf Schlichtmann; Giovanni Squillero (IOLTS, 2022)

Aging Aware Retraining for Memristor-based Neuromorphic Computing. - Wenwen Ye; Grace Li Zhang; Bing Li 005; Ulf Schlichtmann; Cheng Zhuo; Xunzhao Yin (ISCAS, 2022)

A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data. - Tobias Kilian; Markus Hanel; Daniel Tille; Martin Huch; Ulf Schlichtmann (ITC, 2022)

COMPAS: Compiler-assisted Software-implemented Hardware Fault Tolerance for RISC-V. - Uzair Sharif; Daniel Mueller-Gritschneder; Ulf Schlichtmann (MECO, 2022)

Memory Utilization-Based Dynamic Bandwidth Regulation for Temporal Isolation in Multi-Cores. - Ahsan Saeed; Dakshina Dasari; Dirk Ziegenbein; Varun Rajasekaran; Falk Rehm; Michael Pressler; Arne Hamann 001; Daniel Mueller-Gritschneder; Andreas Gerstlauer; Ulf Schlichtmann (RTAS, 2022)

Computer-aided Design Techniques for Flow-based Microfluidic Lab-on-a-chip Systems. - Xing Huang 001; Tsung-Yi Ho; Wenzhong Guo; Bing Li 005; Krishnendu Chakrabarty; Ulf Schlichtmann (ACM Comput. Surv., 2022)

An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors. - Marcel Mettler; Martin Rapp; Heba Khdr; Daniel Mueller-Gritschneder; Jörg Henkel; Ulf Schlichtmann (ACM Trans. Archit. Code Optim., 2022)

Flow-Based Microfluidic Biochips With Distributed Channel Storage: Synthesis, Physical Design, and Wash Optimization. - Xing Huang 001; Wenzhong Guo; Zhisheng Chen 002; Bing Li 005; Tsung-Yi Ho; Ulf Schlichtmann (IEEE Trans. Computers, 2022)

MiniControl 2.0: Co-Synthesis of Flow and Control Layers for Microfluidic Biochips With Strictly Constrained Control Ports. - Xing Huang 001; Tsung-Yi Ho; Zepeng Li; Genggeng Liu; Lu Wang 014; Qingshan Li; Wenzhong Guo; Bing Li 005; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

PathDriver+: Enhanced Path-Driven Architecture Design for Flow-Based Microfluidic Biochips. - Xing Huang 001; Youlin Pan; Grace Li Zhang; Bing Li 005; Wenzhong Guo; Tsung-Yi Ho; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs. - Xiao Moyuan; Tsun-Ming Tseng; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Contamination-Aware Synthesis for Programmable Microfluidic Devices. - Hui-Chieh Yu; Yu-Huei Lin; Zhiyang Chen 006; Bing Li 005; Xing Huang 001; Ulf Schlichtmann; Tsung-Yi Ho; Hailong Yao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

VirtualSync+: Timing Optimization With Virtual Synchronization. - Grace Li Zhang; Bing Li 005; Xing Huang 001; Xunzhao Yin; Cheng Zhuo; Masanori Hashimoto; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V. - Johannes Geier; Lukas Auer; Daniel Mueller-Gritschneder; Uzair Sharif; Ulf Schlichtmann (ASP-DAC, 2023)

Enabling Inter-Product Transfer Learning on MCU Performance Screening. - Nicolò Bellarmino; Riccardo Cantoro; Martin Huch; Tobias Kilian; Ulf Schlichtmann; Giovanni Squillero (ATS, 2023)

Towards Rapid Exploration of Heterogeneous TinyML Systems using Virtual Platforms and TVM's UMA. - Samira Ahmadifarsani; Rafael Stahl; Philipp van Kempen; Daniel Mueller-Gritschneder; Ulf Schlichtmann (CODAI, 2023)

MLonMCU: TinyML Benchmarking with Fast Retargeting. - Philipp van Kempen; Rafael Stahl; Daniel Mueller-Gritschneder; Ulf Schlichtmann (CODAI, 2023)

PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration. - Richard Petri 002; Grace Li Zhang; Yiran Chen 001; Ulf Schlichtmann; Bing Li 005 (DAC, 2023)

CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation. - Amro Eldebiky; Grace Li Zhang; Georg Böcherer; Bing Li 005; Ulf Schlichtmann (DATE, 2023)

VE-FIDES: Designing Trustworthy Supply Chains Using Innovative Fingerprinting Implementations. - Bernhard Lippmann; Joel Hatsch; Stefan Seidl; Detlef Houdeau; Niranjana Papagudi Subrahmanyam; Daniel Schneider; Malek Safieh; Anne Passarelli; Aliza Maftun; Michaela Brunner; Tim Music; Michael Pehl; et al. (DATE, 2023)

Extended Abstract: Monitoring-based Thermal Management for Mixed-Criticality Systems. - Marcel Mettler; Martin Rapp; Heba Khdr; Daniel Mueller-Gritschneder; Jörg Henkel; Ulf Schlichtmann (DATE, 2023)

Efficient Software-Implemented HW Fault Tolerance for TinyML Inference in Safety-critical Applications. - Uzair Sharif; Daniel Mueller-Gritschneder; Rafael Stahl; Ulf Schlichtmann (DATE, 2023)

Class-based Quantization for Neural Networks. - Wenhao Sun; Grace Li Zhang; Huaxi Gu; Bing Li 005; Ulf Schlichtmann (DATE, 2023)

SteppingNet: A Stepping Neural Network with Incremental Accuracy Enhancement. - Wenhao Sun; Grace Li Zhang; Xunzhao Yin; Cheng Zhuo; Huaxi Gu; Bing Li 005; Ulf Schlichtmann (DATE, 2023)

XRing: A Crosstalk-Aware Synthesis Method for Wavelength-Routed Optical Ring Routers. - Zhidan Zheng; Mengchu Li; Tsun-Ming Tseng; Ulf Schlichtmann (DATE, 2023)

An efficient High-Volume Production Performance Screening using On-Chip Ring Oscillators. - Tobias Kilian; Abhishek Sengupta; Daniel Tille; Martin Huch; Ulf Schlichtmann (DFT, 2023)

Memory Latency Distribution-Driven Regulation for Temporal Isolation in MPSoCs. - Ahsan Saeed; Denis Hoornaert; Dakshina Dasari; Dirk Ziegenbein; Daniel Mueller-Gritschneder; Ulf Schlichtmann; Andreas Gerstlauer; Renato Mancuso 001 (ECRTS, 2023)

Semi-Supervised Deep Learning for Microcontroller Performance Screening. - Nicolò Bellarmino; Riccardo Cantoro; Martin Huch; Tobias Kilian; Ulf Schlichtmann; Giovanni Squillero (ETS, 2023)

GAT-based Concentration Prediction for Random Microfluidic Mixers with Multiple Input Flow Rates. - Weiqing Ji; Hailong Yao; Tsung-Yi Ho; Ulf Schlichtmann; Xia Yin (ACM Great Lakes Symposium on VLSI, 2023)

SOAER: Self-Obstacle Avoiding Escape Routing for Paper-Based Digital Microfluidic Biochips. - Weiqing Ji; Xingcheng Yao; Hailong Yao; Tsung-Yi Ho; Ulf Schlichtmann; Xia Yin (ACM Great Lakes Symposium on VLSI, 2023)

MonTM: Monitoring-Based Thermal Management for Mixed-Criticality Systems. - Marcel Mettler; Martin Rapp; Heba Khdr; Daniel Mueller-Gritschneder; Jörg Henkel; Ulf Schlichtmann (PARMA-DITAM, 2023)

A Novel and Efficient Block-Based Programming for ReRAM-Based Neuromorphic Computing. - Wei-Lun Chen; Fang-Yi Gu; Ing-Chao Lin; Grace Li Zhang; Bing Li 005; Ulf Schlichtmann (ICCAD, 2023)

NeuroEscape: Ordered Escape Routing via Monte-Carlo Tree Search and Neural Network. - Zhiyang Chen 006; Tsung-Yi Ho; Ulf Schlichtmann; Datao Chen; Mingyu Liu; Hailong Yao; Xia Yin (ICCAD, 2023)

ARMM: Adaptive Reliability Quantification Model of Microfluidic Designs and its Graph-Transformer-Based Implementation. - Siyuan Liang; Meng Lian 001; Mengchu Li; Tsun-Ming Tseng; Ulf Schlichtmann; Tsung-Yi Ho (ICCAD, 2023)

FXT-Route: Efficient High-Performance PCB Routing with Crosstalk Reduction Using Spiral Delay Lines. - Meng Lian 001; Yushen Zhang; Mengchu Li; Tsun-Ming Tseng; Ulf Schlichtmann (ISPD, 2023)

Feature Selection for Cost Reduction In MCU Performance Screening. - Nicolò Bellarmino; Riccardo Cantoro; Martin Huch; Tobias Kilian; Ulf Schlichtmann; Giovanni Squillero (LATS, 2023)

Biologically Plausible Learning on Neuromorphic Hardware Architectures. - Christopher Wolters; Brady Taylor; Edward Hanson; Xiaoxuan Yang 001; Ulf Schlichtmann; Yiran Chen 001 (MWSCAS, 2023)

Implementation of a Robust and Power-Efficient Nonlinear 64-QAM Demapper using In-Memory Computing. - Amro Eldebiky; Georg Böcherer; Maximilian Schädler; Stefano Calabrò; Bing Li 005; Ulf Schlichtmann (OFC, 2023)

Area-Efficient Neural Network CD Equalizer for 4×200Gb/s PAM4 CWDM4 Systems. - Bo Liu; Christian Blümm; Stefano Calabrò; Bing Li 005; Ulf Schlichtmann (OFC, 2023)

Fused Depthwise Tiling for Memory Optimization in TinyML Deep Neural Network Inference. - Rafael Stahl; Daniel Mueller-Gritschneder; Ulf Schlichtmann (CoRR, 2023)

Expressivity Enhancement with Efficient Quadratic Neurons for Convolutional Neural Networks. - Chuangtao Chen 001; Grace Li Zhang; Xunzhao Yin; Cheng Zhuo; Ulf Schlichtmann; Bing Li 005 (CoRR, 2023)

Design Automation for Continuous-Flow Lab-on-a-Chip Systems: A One-Pass Paradigm. - Xing Huang 001; Youlin Pan; Zhen Chen; Wenzhong Guo; Lu Wang 014; Qingshan Li; Robert Wille; Tsung-Yi Ho; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Machine Learning in Advanced IC Design: A Methodological Survey. - Tinghuan Chen; Grace Li Zhang; Bei Yu 001; Bing Li 005; Ulf Schlichtmann (IEEE Des. Test, 2023)

Guest Editors' Introduction: Special Issue on Machine Learning for CAD/EDA. - Ulf Schlichtmann; Bing Li 005; Bei Yu 001; Raviv Gal (IEEE Des. Test, 2023)

Training PPA Models for Embedded Memories on a Low-data Diet. - Felix Last; Ulf Schlichtmann (ACM Trans. Design Autom. Electr. Syst., 2023)

Ferroelectric Ternary Content Addressable Memories for Energy-Efficient Associative Search. - Xunzhao Yin; Yu Qian; Mohsen Imani; Kai Ni 004; Chao Li 065; Grace Li Zhang; Bing Li 005; Ulf Schlichtmann; Cheng Zhuo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Integrated Test Module Design for Microfluidic Large-Scale Integration. - Mengchu Li; Yushen Zhang; Ju Young Lee; Hudson Gasvoda; Ismail Emre Araci; Tsun-Ming Tseng; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Performance Screening Using Functional Path Ring Oscillators. - Tobias Kilian; Daniel Tille; Martin Huch; Markus Hanel; Ulf Schlichtmann (IEEE Trans. Very Large Scale Integr. Syst., 2023)

BRoCoM: A Bayesian Framework for Robust Computing on Memristor Crossbar. - Di Gao; Zeyu Yang; Qingrong Huang; Grace Li Zhang; Xunzhao Yin; Bing Li 005; Ulf Schlichtmann; Cheng Zhuo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Multilabel Active Learning Framework for Microcontroller Performance Screening. - Nicolò Bellarmino; Riccardo Cantoro; Martin Huch; Tobias Kilian; Raffaele Martone; Ulf Schlichtmann; Giovanni Squillero (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Logic Design of Neural Networks for High-Throughput and Low-Power Applications. - Kangwei Xu; Grace Li Zhang; Ulf Schlichtmann; Bing Li 005 (ASPDAC, 2024)

muRISCV-NN: Challenging Zve32x Autovectorization with TinyML Inference Library for RISC-V Vector Extension. - Philipp van Kempen; Jefferson Parker Jones; Daniel Mueller-Gritschneder; Ulf Schlichtmann (CF (Companion), 2024)

MuDSE: GA-ILP-based Framework for Automated Deployment of Multiple DNNs on Heterogeneous Mixed-Criticality Systems. - Alexander Hoffman; Ala Fnayou; Fedor Smirnov; Daniel Mueller-Gritschneder; Ulf Schlichtmann (COINS, 2024)

Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI). - Mengchu Li; Hanchen Gu; Yushen Zhang; Siyuan Liang; Hudson Gasvoda; Rana Altay; Ismail Emre Araci; Tsun-Ming Tseng; Tsung-Yi Ho; Ulf Schlichtmann (DAC, 2024)

LaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design. - Siyuan Liang; Yushen Zhang; Rana Altay; Hudson Gasvoda; Mengchu Li; Ismail Emre Araci; Tsun-Ming Tseng; Ulf Schlichtmann; Tsung-Yi Ho (DAC, 2024)

Multi-Resonance Mesh-Based Wavelength-Routed Optical Networks-on-Chip. - Zhidan Zheng; Liaoyuan Cheng; Kanta Arisawa; Qingyu Li; Alexandre Truppel; Shigeru Yamashita; Tsun-Ming Tseng; Ulf Schlichtmann (DAC, 2024)

Computational and Storage Efficient Quadratic Neurons for Deep Neural Networks. - Chuangtao Chen 001; Grace Li Zhang; Xunzhao Yin; Cheng Zhuo; Ulf Schlichtmann; Bing Li 005 (DATE, 2024)

A FeFET-based Time-Domain Associative Memory for Multi-bit Similarity Computation. - Qingrong Huang; Hamza Errahmouni Barkam; Zeyu Yang; Jianyi Yang 003; Thomas Kämpfe; Kai Ni 004; Grace Li Zhang; Bing Li 005; Ulf Schlichtmann; Mohsen Imani; Cheng Zhuo; Xunzhao Yin (DATE, 2024)

PathDriver-Wash: A Path-Driven Wash Optimization Method for Continuous-Flow Lab-on-a-Chip Systems. - Xing Huang 001; Jiaxuan Wang; Zhiwen Yu 001; Bin Guo 001; Tsung-Yi Ho; Ulf Schlichtmann; Krishnendu Chakrabarty (DATE, 2024)

ScanCamouflage: Obfuscating Scan Chains with Camouflaged Sequential and Logic Gates. - Tarik Ibrahimpasic; Grace Li Zhang; Michaela Brunner; Georg Sigl; Bing Li 005; Ulf Schlichtmann (DATE, 2024)

OplixNet: Towards Area-Efficient Optical Split-Complex Networks with Real-to-Complex Data Assignment and Knowledge Distillation. - Ruidi Qiu; Amro Eldebiky; Grace Li Zhang; Xunzhao Yin; Cheng Zhuo; Ulf Schlichtmann; Bing Li 005 (DATE, 2024)

Seal5: Semi-Automated LLVM Support for RISC-V ISA Extensions Including Autovectorization. - Philipp van Kempen; Mathis Salmen; Daniel Mueller-Gritschneder; Ulf Schlichtmann (DSD, 2024)

Embedded Feature Selection in MCU Performance Screening. - Nicolò Bellarmino; Riccardo Cantoro; Martin Huch; Tobias Kilian; Ulf Schlichtmann; Giovanni Squillero (DTTIS, 2024)

Minimizing Worst-Case Data Transmission Cycles in Wavelength-Routed Optical NoC through Bandwidth Allocation. - Liaoyuan Cheng; Mengchu Li; Tsun-Ming Tseng; Ulf Schlichtmann (ICCAD, 2024)

BasisN: Reprogramming-Free RRAM-Based In-Memory-Computing by Basis Combination for Deep Neural Networks. - Amro Eldebiky; Grace Li Zhang; Xunzhao Yin; Cheng Zhuo; Ing-Chao Lin; Ulf Schlichtmann; Bing Li 005 (ICCAD, 2024)

RABER: Reliability-Aware Bayesian-Optimization-based Control Layer Escape Routing for Flow-based Microfluidics. - Siyuan Liang; Rongliang Fu; Mengchu Li; Tsun-Ming Tseng; Ulf Schlichtmann; Tsung-Yi Ho (ICCAD, 2024)

Toward Early Stage Dynamic Power Estimation: Exploring Alternative Machine Learning Methods and Simulation Schemes. - Philipp Fengler; Sani R. Nassif; Ulf Schlichtmann (ISQED, 2024)

MuNAS: TinyML Network Architecture Search Using Goal Attainment and Reinforcement Learning. - Alexander Hoffman; Ulf Schlichtmann; Daniel Mueller-Gritschneder (MECO, 2024)

AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design. - Ruidi Qiu; Grace Li Zhang; Rolf Drechsler; Ulf Schlichtmann; Bing Li 005 (MLCAD, 2024)

Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models. - Kangwei Xu; Grace Li Zhang; Xunzhao Yin; Cheng Zhuo; Ulf Schlichtmann; Bing Li 005 (MLCAD, 2024)

ZuSE-KI-Mobil AI Chip Design Platform: An Overview. - Shaown Mojumder; Simon Friedrich; Emil Matús; Gerhard P. Fettweis; Matthias Lüders; Martin Friedrich; Oliver Renke; Holger Blume; Julian Höfer; Patrick Schmidt; Jürgen Becker 001; Darius Grantz; et al. (NorCAS, 2024)

EncodingNet: A Novel Encoding-based MAC Design for Efficient Neural Network Acceleration. - Bo Liu; Grace Li Zhang; Xunzhao Yin; Ulf Schlichtmann; Bing Li 005 (CoRR, 2024)

Memory Is All You Need: An Overview of Compute-in-Memory Architectures for Accelerating Large Language Model Inference. - Christopher Wolters; Xiaoxuan Yang 001; Ulf Schlichtmann; Toyotaro Suzumura (CoRR, 2024)

LiveMind: Low-latency Large Language Models with Simultaneous Inference. - Chuangtao Chen 001; Grace Li Zhang; Xunzhao Yin; Cheng Zhuo; Ulf Schlichtmann; Bing Li 005 (CoRR, 2024)

Classification-Based Automatic HDL Code Generation Using LLMs. - Wenhao Sun; Bing Li 005; Grace Li Zhang; Xunzhao Yin; Cheng Zhuo; Ulf Schlichtmann (CoRR, 2024)

LLM-Aided Efficient Hardware Design Automation. - Kangwei Xu; Ruidi Qiu; Zhuorui Zhao; Grace Li Zhang; Ulf Schlichtmann; Bing Li 005 (CoRR, 2024)

Control-Logic Synthesis of Fully Programmable Valve Array Using Reinforcement Learning. - Xing Huang 001; Huayang Cai; Wenzhong Guo; Genggeng Liu; Tsung-Yi Ho; Krishnendu Chakrabarty; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

CorrectNet+: Dealing With HW Non-Idealities in In-Memory-Computing Platforms by Error Suppression and Compensation. - Amro Eldebiky; Grace Li Zhang; Georg Böcherer; Bing Li 005; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Aging-Aware Energy-Efficient Task Deployment of Heterogeneous Multicore Systems. - Yu-Guang Chen; Chieh-Shih Wang; Ing-Chao Lin; Zheng-Wei Chen; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

GNN-Based Concentration Prediction With Variable Input Flow Rates for Microfluidic Mixers. - Weiqing Ji; Xingzhuo Guo; Shouan Pan; Fei Long; Tsung-Yi Ho; Ulf Schlichtmann; Hailong Yao (IEEE Trans. Biomed. Circuits Syst., 2024)

A 3D Hybrid Optical-Electrical NoC Using Novel Mapping Strategy Based DCNN Dataflow Acceleration. - Bowen Zhang 004; Huaxi Gu; Grace Li Zhang; Yintang Yang; Ziteng Ma; Ulf Schlichtmann (IEEE Trans. Parallel Distributed Syst., 2024)

Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions. - Conrad Foik; Robert Kunzelmann; Daniel Mueller-Gritschneder; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

On the Relation Between Reliability and Entropy in Physical Unclonable Functions. - Vasilii Kulagin; Sergio Vinagrero Gutierrez; Tobias Kilian; Daniel Tille; Ulf Schlichtmann; Giorgio Di Natale; Elena-Ioana Vatajelu (IEEE Des. Test, 2024)

A Hardware Friendly Variation-Tolerant Framework for RRAM-Based Neuromorphic Computing. - Fang-Yi Gu; Cheng-Han Yang; Ing-Chao Lin; Da-Wei Chang; Darsen D. Lu; Ulf Schlichtmann (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Dynamic Topology-Aware Flow Path Construction and Scheduling Optimization for Multilayered Continuous-Flow Microfluidic Biochips. - Meng Lian 001; Shucheng Yang; Mengchu Li; Tsun-Ming Tseng; Ulf Schlichtmann (ASP-DAC, 2025)

CPONoC: Critical Path-aware Physical Implementation for Optical Networks-on-Chip. - Yan-Ting Chen; Zhidan Zheng; Shao-Yun Fang; Tsun-Ming Tseng; Ulf Schlichtmann (ASP-DAC, 2025)

An Efficient General-Purpose Optical Accelerator for Neural Networks. - Sijie Fei; Amro Eldebiky; Grace Li Zhang; Bing Li 005; Ulf Schlichtmann (ASP-DAC, 2025)

HyperG: Multilevel GPU-Accelerated k-way Hypergraph Partitioner. - Wan-Luan Lee; Dian-Lun Lin; Cheng-Hsiang Chiu; Ulf Schlichtmann; Tsung-Wei Huang (ASP-DAC, 2025)

3M-DeSyn: Design Synthesis for Multi-Layer 3D-Printed Microfluidics with Timing and Volumetric Control. - Yushen Zhang; Dragan Raseta; Tsun-Ming Tseng; Ulf Schlichtmann (ASP-DAC, 2025)

A Backup Resource Customization and Allocation Method for Wavelength-Routed Optical Networks-on-Chip Topologies. - Zhidan Zheng; You-Jen Chang; Liaoyuan Cheng; Tsun-Ming Tseng; Ulf Schlichtmann (ASP-DAC, 2025)

RepFC: Universal Structural Reparametrization Block for High Performance, Lightweight Deep Neural Networks. - Shambhavi Balamuthu Sampath; Judeson Anthony Fernando; Moritz Thoma; Nael Fasfous; Lukas Frickenstein; Pierpaolo Morì; Manoj Rohit Vemparala; Alexander Frickenstein; Ulf Schlichtmann; Walter Stechele (CVPR Workshops, 2025)

Uncertainty Aware Training to Improve Uncertainty Active Learning for Semantic Segmentation. - Moritz Thoma; Tobias Preintner; Emad Aghajanzadeh; Shambhavi Balamuthu Sampath; Pierpaolo Morì; Nael Fasfous; Manoj Rohit Vemparala; Alexander Frickenstein; Daniel Mueller-Gritschneder; Ulf Schlichtmann (CVPR Workshops, 2025)

FLAR-SVD: Fast and Latency-Aware Singular Value Decomposition for Model Compression. - Moritz Thoma; Jorge Villasante; Emad Aghajanzadeh; Shambhavi Balamuthu Sampath; Pierpaolo Morì; Maximilian Groetzinger; Daniil Dylkin; Manoj Rohit Vemparala; Nael Fasfous; Alexander Frickenstein; Daniel Mueller-Gritschneder; Ulf Schlichtmann (CVPR Workshops, 2025)

Rapid Fault Injection Simulation by Hash-Based Differential Fault Effect Equivalence Checks. - Johannes Geier; Leonidas Kontopoulos; Daniel Mueller-Gritschneder; Ulf Schlichtmann (DATE, 2025)

Multi-Partner Project: Advancing the EDA Tools Landscape for the European RISC-V Ecosystem in TRISTAN. - Fatma Jebali; Caaliph Andriamisaina; Mathieu Jan; Wolfgang Ecker; Florian Egert; Bernhard Fischer; Alessio Burrello; Daniele Jahier Pagliari; Sara Vinco; Giuseppe Tagliavini; Ingo Feldner; Andreas Mauderer; et al. (DATE, 2025)

Loading-Aware Mixing-Efficient Sample Preparation on Programmable Microfluidic Device. - Debraj Kundu; Tsun-Ming Tseng; Shigeru Yamashita; Ulf Schlichtmann (DATE, 2025)

CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design. - Ruidi Qiu; Grace Li Zhang; Rolf Drechsler; Ulf Schlichtmann; Bing Li 005 (DATE, 2025)

Multi-Partner Project: Open-Source Design Tools for Co-Development of AI Algorithms and AI Chips: (Initial Stage). - Mehdi B. Tahoori; Jürgen Becker 001; Jörg Henkel; Wolfgang Kunz; Ulf Schlichtmann; Georg Sigl; Jürgen Teich; Norbert Wehn (DATE, 2025)

SRing: A Sub-Ring Construction Method for Application-Specific Wavelength-Routed Optical NoCs. - Zhidan Zheng; Meng Lian 001; Mengchu Li; Tsun-Ming Tseng; Ulf Schlichtmann (DATE, 2025)

Large Language Models (LLMs) for Verification, Testing, and Design. - Chandan Kumar Jha 001; Muhammad Hassan 001; Khushboo Qayyum; Sallar Ahmadi-Pour; Kangwei Xu; Ruidi Qiu; Jason Blocklove; Luca Collini; Andre Nakkab; Ulf Schlichtmann; Grace Li Zhang; Ramesh Karri; et al. (ETS, 2025)

A Lifetime Extension Framework for Communication-Intensive Systems Based on Wavelength-Routed Optical Networks-on-Chip. - Zhidan Zheng; Liaoyuan Cheng; Jeng-De Chang; Tsun-Ming Tseng; Ing-Chao Lin; Ulf Schlichtmann (ACM Great Lakes Symposium on VLSI, 2025)

Accurate Fault Detection for Wavelength-Routed Optical Networks-on-Chip Under Thermal Variation. - Yu Zhou; Zhidan Zheng; Liaoyuan Cheng; Jiahong Huang; Tsun-Ming Tseng; Ulf Schlichtmann (ACM Great Lakes Symposium on VLSI, 2025)

Enabling Machine Learning for Power Modeling via Artificial Netlist Generation. - Philipp Fengler; Junpeng Chen; Sani R. Nassif; Ulf Schlichtmann (ISCAS, 2025)

Obstacle-Aware Synthesis of the Bus Topology Considering Wire Length Minimization. - Meng Lian 001; Yushen Zhang; Mengchu Li; Tsun-Ming Tseng; Shejun Sun; Ulf Schlichtmann (ISQED, 2025)

Paradigm-Based Automatic HDL Code Generation Using LLMs. - Wenhao Sun; Bing Li 005; Grace Li Zhang; Xunzhao Yin; Cheng Zhuo; Ulf Schlichtmann (ISQED, 2025)

VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency. - Zhuorui Zhao; Ruidi Qiu; Ing-Chao Lin; Grace Li Zhang; Bing Li 005; Ulf Schlichtmann (ISQED, 2025)

COSMO: COmpressed Sensing for Models and Logging Optimization in MCU Performance Screening. - Nicolò Bellarmino; Riccardo Cantoro; Sophie M. Fosson; Martin Huch; Tobias Kilian; Ulf Schlichtmann; Giovanni Squillero (IEEE Trans. Computers, 2025)

Deep Learning Strategies for Labeling and Accuracy Optimization in Microcontroller Performance Screening. - Nicolò Bellarmino; Riccardo Cantoro; Martin Huch; Tobias Kilian; Ulf Schlichtmann; Giovanni Squillero (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Manufacturing Cycle Time Optimization for Inkjet-Printed Electronics. - Meng Lian 001; Hu Peng; Mengchu Li; Yushen Zhang; Tsun-Ming Tseng; Bernhard Wolfrum; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Combinatorial-Coding-Based High-Performance Microfluidic Control Multiplexer: Design, Synthesis, and Adaptation. - Siyuan Liang; Mengchu Li; Tsun-Ming Tseng; Ulf Schlichtmann; Tsung-Yi Ho (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis. - Kangwei Xu; Bing Li 005; Grace Li Zhang; Ulf Schlichtmann (CoRR, 2025)

A Scalable 2T-1FeFET-Based Content Addressable Memory Design for Energy Efficient Data Search. - Jiahao Cai; Hamza Errahmouni Barkam; Mohsen Imani; Kai Ni 004; Grace Li Zhang; Bing Li 005; Ulf Schlichtmann; Cheng Zhuo; Xunzhao Yin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

A Homogeneous FeFET-Based Time-Domain Compute-in-Memory Fabric for Matrix-Vector Multiplication and Associative Search. - Xunzhao Yin; Qingrong Huang; Hamza Errahmouni Barkam; Franz Müller 001; Shan Deng; Alptekin Vardar; Sourav De 002; Zhouhang Jiang; Mohsen Imani; Ulf Schlichtmann; Xiaobo Sharon Hu; Cheng Zhuo; et al. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

A High-Level Compiler Integration Approach for Deep Learning Accelerators Supporting Abstraction and Optimization. - Samira Ahmadifarsani; Daniel Mueller-Gritschneder; Ulf Schlichtmann (CoRR, 2025)