New structures for very high-frequency CMOS clock dividers. - Ullas Singh; Michael Green (ISCAS (4), 2001)

Dynamics of high-frequency CMOS dividers. - Ullas Singh; Michael Green (ISCAS (5), 2002)

Design of CMOS CML circuits for high-speed broadband communications. - Michael M. Green; Ullas Singh (ISCAS (2), 2003)

High-frequency CML clock dividers in 0.13-μm CMOS operating up to 38 GHz. - Ullas Singh; Michael M. Green (IEEE J. Solid State Circuits, 2005)

A 34 Gb/s Distributed 2: 1 MUX and CMU Using 0.18$muhbox m$CMOS. - Ullas Singh; Lijun Li; Michael M. Green (IEEE J. Solid State Circuits, 2006)

21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber. - Jun Cao 001; Bo Zhang 029; Ullas Singh; Delong Cui; Anand Vasani; Adesh Garg; Wei Zhang; Namik Kocaman; Deyi Pi; Bharath Raghavan; Hui Pan 002; Ichiro Fujimori; et al. (ISSCC, 2009)

A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber. - Jun Cao 001; Bo Zhang 029; Ullas Singh; Delong Cui; Anand Vasani; Adesh Garg; Wei Zhang; Namik Kocaman; Deyi Pi; Bharath Raghavan; Hui Pan 002; Ichiro Fujimori; et al. (IEEE J. Solid State Circuits, 2010)

11.3Gb/s CMOS SONET-compliant transceiver for both RZ and NRZ applications. - Namik Kocaman; Adesh Garg; Bharath Raghavan; Delong Cui; Anand Vasani; Keith Tang; Deyi Pi; Haitao Tong; Siavash Fallahi; Wei Zhang; Ullas Singh; Jun Cao 001; et al. (ISSCC, 2011)

11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications. - Namik Kocaman; Adesh Garg; Bharath Raghavan; Delong Cui; Anand Vasani; Keith Tang; Deyi Pi; Haitao Tong; Siavash Fallahi; Wei Zhang; Ullas Singh; Jun Cao 001; et al. (IEEE J. Solid State Circuits, 2011)

A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission. - Delong Cui; Bharath Raghavan; Ullas Singh; Anand Vasani; Zhi Chao Huang; Deyi Pi; Mehdi Khanpour; Ali Nazemi; Hassan Maarefi; Tamer A. Ali 001; Nick Huang; Wei Zhang; et al. (ISSCC, 2012)

A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission. - Delong Cui; Bharath Raghavan; Ullas Singh; Anand Vasani; Zhi Chao Huang; Deyi Pi; Mehdi Khanpour; Ali Nazemi; Hassan Maarefi; Wei Zhang; Tamer A. Ali 001; Nick Huang; et al. (IEEE J. Solid State Circuits, 2012)

A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS. - Bharath Raghavan; Delong Cui; Ullas Singh; Hassan Maarefi; Dave Pi; Anand Vasani; Zhi Chao Huang; Afshin Momtaz; Jun Cao 001 (ISSCC, 2013)

An 8.5-11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition. - Namik Kocaman; Siavash Fallahi; Mahyar Kargar; Mehdi Khanpour; Ali Nazemi; Ullas Singh; Afshin Momtaz (IEEE J. Solid State Circuits, 2013)

A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS. - Bharath Raghavan; Delong Cui; Ullas Singh; Hassan Maarefi; Deyi Pi; Anand Vasani; Zhi Chao Huang; Burak Çatli; Afshin Momtaz; Jun Cao 001 (IEEE J. Solid State Circuits, 2013)

2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS. - Ullas Singh; Adesh Garg; Bharath Raghavan; Nick Huang; Heng Zhang; Zhi Huang; Afshin Momtaz; Jun Cao 001 (ISSCC, 2014)

A quad-channel 112-128 Gb/s coherent transmitter in 40 nm CMOS. - Adesh Garg; Ullas Singh; Nick Huang; Wayne Wong; Bin Liu; Zhi Chao Huang; Afshin Momtaz; Jun Cao 001 (VLSIC, 2014)

A 780 mW 4 × 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS. - Ullas Singh; Adesh Garg; Bharath Raghavan; Nick Huang; Heng Zhang; Zhi Chao Huang; Afshin Momtaz; Jun Cao 001 (IEEE J. Solid State Circuits, 2014)

3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS. - Ali Nazemi; Kangmin Hu; Burak Çatli; Delong Cui; Ullas Singh; Tim He; Zhi Chao Huang; Bo Zhang 029; Afshin Momtaz; Jun Cao 001 (ISSCC, 2015)

A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS. - Namik Kocaman; Tamer A. Ali 001; Lakshmi P. Rao; Ullas Singh; Mohammed M. Abdul-Latif; Yang Liu; Amr Amin Hafez; Henry Park; Anand Vasani; Zhi Huang; Arvindh Iyer; Bo Zhang 029; et al. (IEEE J. Solid State Circuits, 2016)

An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology. - Namik Kocaman; Ullas Singh; Bharath Raghavan; Arvindh Iyer; Kumar Thasari; Saurabh Surana; Jun Won Jung; Jaehun Jeong; Heng Zhang; Anand Vasani; Yonghyun Shim; Zhi Huang; et al. (ISSCC, 2022)

18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS. - Guansheng Li; Adesh Garg; Tim He; Ullas Singh; Jiawen Zhang; Lakshmi P. Rao; Chang Liu; Meisam Honarvar Nazari; Yang Liu; Yong Liu; Heng Zhang; Tamer A. Ali 001; et al. (ISSCC, 2024)