Faster Optimal Single-Row Placement with Fixed Ordering. - Ulrich Brenner; Jens Vygen (DATE, 2000)

Worst-case ratios of networks in the rectilinear plane. - Ulrich Brenner; Jens Vygen (Networks, 2001)

An effective congestion-driven placement framework. - Ulrich Brenner; André Rohe (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Almost optimum placement legalization by minimum cost flow and dynamic programming. - Ulrich Brenner; Anna Pauli; Jens Vygen (ISPD, 2004)

Legalizing a placement with minimum total movement. - Ulrich Brenner; Jens Vygen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Faster and better global placement by a new transportation algorithm. - Ulrich Brenner; Markus Struzyna (DAC, 2005)

Theory and Practice of VLSI Placement - Ulrich Brenner (2006)

A faster polynomial algorithm for the unbalanced Hitchcock transportation problem. - Ulrich Brenner (Oper. Res. Lett., 2008)

BonnPlace: Placement of Leading-Edge Chips by Advanced Combinatorial Algorithms. - Ulrich Brenner; Markus Struzyna; Jens Vygen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Analytical Methods in Placement. - Ulrich Brenner; Jens Vygen (Handbook of Algorithms for Physical Design Automation, 2008)

VLSI legalization with minimum perturbation by iterative augmentation. - Ulrich Brenner (DATE, 2012)

BonnPlace Legalization: Minimizing Movement by Iterative Augmentation. - Ulrich Brenner (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

BonnPlace: A Self-Stabilizing Placement Framework. - Ulrich Brenner; Anna Hermann; Nils Hoppmann; Philipp Ochsendorf (ISPD, 2015)

Faster Adder Circuits for Inputs with Prescribed Arrival Times. - Ulrich Brenner; Anna Hermann (CoRR, 2017)

γ-Soft packings of rectangles. - Ulrich Brenner (Comput. Geom., 2018)

Faster Carry Bit Computation for Adder Circuits with Prescribed Arrival Times. - Ulrich Brenner; Anna Hermann (ACM Trans. Algorithms, 2019)

Delay Optimization of Combinational Logic by AND-OR Path Restructuring. - Ulrich Brenner; Anna Silvanus (ASP-DAC, 2022)

Constructing depth-optimum circuits for adders and And-Or paths. - Ulrich Brenner; Anna Silvanus; Jannik Silvanus (Discret. Appl. Math., 2022)

BonnLogic: Delay optimization by And-Or Path restructuring. - Ulrich Brenner; Anna Silvanus (Integr., 2023)

Bounds on soft rectangle packing ratios. - Judith Brecklinghaus; Ulrich Brenner; Oliver Kiss (Comput. Geom., 2024)

Faster Linear-Size And-Or Path and Adder Circuits. - Ulrich Brenner; Anna Silvanus (CoRR, 2024)

Delay-Optimum Adder Circuits with Linear Size. - Ulrich Brenner; Benjamin David Görg (CoRR, 2024)