On the single-chip implementation of a Hiperlan/2 and IEEE 802.11a capable modem. - Eckhard Grass; Klaus Tittelbach-Helmrich; Ulrich Jagdhold; Alfonso Troya; Gunther Lippert; Olaf Krüger; Jens Lehmann 002; Koushik Maharatna; Kai F. Dombrowski; Norbert Fiebig; Rolf Kraemer; Petri Mähönen (IEEE Wirel. Commun., 2001)

A novel 64-point FF/IFFT processor for IEEE 802.11(a) standard. - Koushik Maharatna; Eckhard Grass; Ulrich Jagdhold (ICASSP (2), 2003)

A CORDIC like processor for computation of arctangent and absolute magnitude of a vector. - Koushik Maharatna; Alfonso Troya; Milos Krstic; Eckhard Grass; Ulrich Jagdhold (ISCAS (2), 2004)

A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM. - Koushik Maharatna; Eckhard Grass; Ulrich Jagdhold (IEEE J. Solid State Circuits, 2004)

Efficient Inner Receiver Design for OFDM-Based WLAN Systems: Algorithm and Architecture. - Alfonso Troya; Koushik Maharatna; Milos Krstic; Eckhard Grass; Ulrich Jagdhold; Rolf Kraemer (IEEE Trans. Wirel. Commun., 2007)

Low-Power VLSI Implementation of the Inner Receiver for OFDM-Based WLAN Systems. - Alfonso Troya; Koushik Maharatna; Milos Krstic; Eckhard Grass; Ulrich Jagdhold; Rolf Kraemer (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

HDL-Synthese und Simulation von Hochgeschwindigkeits-Digitalschaltungen mit gemischten CMOS- und ECL-Bibliotheken. - Frank Winkler 001; Gerald Kell; Oliver Schrape; Hans Gustat; Ulrich Jagdhold (MBMV, 2009)

An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis. - Oliver Schrape; Frank Winkler 001; Steffen Zeidler 001; Markus Petri; Eckhard Grass; Ulrich Jagdhold (PATMOS, 2010)