A Synthesis System For Bus-Based Wavefront Array Architectures. - Reiner W. Hartenstein; Jürgen Becker 001; Michael Herz; Rainer Kress 002; Ulrich Nageldinger (ASAP, 1996)

A Partitioning Programming Environment for a Novel Parallel Architecture. - Reiner W. Hartenstein; Jürgen Becker 001; Michael Herz; Rainer Kress 002; Ulrich Nageldinger (IPPS, 1996)

A Novel Universal Sequencer Hardware. - Reiner W. Hartenstein; Jürgen Becker 001; Michael Herz; Ulrich Nageldinger (ARCS, 1997)

A Novel Sequencer Hardware for Application Specific Computing. - Reiner W. Hartenstein; Jürgen Becker 001; Michael Herz; Ulrich Nageldinger (ASAP, 1997)

Data scheduling to increase performance of parallel accelerators. - Reiner W. Hartenstein; Jürgen Becker 001; Michael Herz; Ulrich Nageldinger (FPL, 1997)

An operating system for custom computing machines based on the Xputer paradigm. - Rainer Kress 002; Reiner W. Hartenstein; Ulrich Nageldinger (FPL, 1997)

Parallelization in Co-Compilation for Configurable Accelerators. - Jürgen Becker 001; Reiner W. Hartenstein; Michael Herz; Ulrich Nageldinger (ASP-DAC, 1998)

Exploiting Contemporary Memory Techniques in Reconfigurable Accelerators. - Reiner W. Hartenstein; Michael Herz; Thomas Hoffmann 001; Ulrich Nageldinger (FPL, 1998)

On Reconfigurable Co-processing Units. - Reiner W. Hartenstein; Michael Herz; Thomas Hoffmann 001; Ulrich Nageldinger (IPPS/SPDP Workshops, 1998)

Mapping Applications onto Reconfigurable Kress Arrays. - Reiner W. Hartenstein; Michael Herz; Thomas Hoffmann 001; Ulrich Nageldinger (FPL, 1999)

An Internet Based Development Framework for Reconfigurable Computing. - Reiner W. Hartenstein; Michael Herz; Ulrich Nageldinger; Thomas Hoffmann 001 (FPL, 1999)

XMDS: The Xputer Multimedia Development System. - Michael Herz; Thomas Hoffmann 001; Ulrich Nageldinger; Christian Schreiber (HICSS, 1999)

Interfacing the MoM-PDA to an Internet-based Development System. - Michael Herz; Thomas Hoffmann 001; Ulrich Nageldinger; Christian Schreiber (HICSS, 1999)

KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array. - Reiner W. Hartenstein; Michael Herz; Thomas Hoffmann 001; Ulrich Nageldinger (ASP-DAC, 2000)

Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract). - Reiner W. Hartenstein; Michael Herz; Thomas Hoffmann 001; Ulrich Nageldinger (FPGA, 2000)

Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures. - Reiner W. Hartenstein; Michael Herz; Thomas Hoffmann 001; Ulrich Nageldinger (FPL, 2000)

Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures. - Reiner W. Hartenstein; Thomas Hoffmann 001; Ulrich Nageldinger (PATMOS, 2000)

Coarse-grained reconfigurable architecture design space exploration. - Ulrich Nageldinger (2001)

Integration of Reconfigurable Hardware into System-Level Design. - Klaus Buchenrieder; Ulrich Nageldinger; Andreas Pyttel; Alexander Sedlmeier (FPL, 2002)

System Prototyping by Integration of Reconfigurable Hardware into a Heterogeneous System Model. - Klaus Buchenrieder; Ulrich Nageldinger; Andreas Pyttel; Alexander Sedlmeier (IEEE International Workshop on Rapid System Prototyping, 2002)

Reducing the Power Consumption of FPGAs through Retiming. - Robert Fischer 002; Klaus Buchenrieder; Ulrich Nageldinger (ECBS, 2005)

A Low-Cost Realization of an Adaptable Protocol Processing Unit. - Maik Boden; Alex Gleich; Steffen Rülke; Ulrich Nageldinger (IPDPS, 2005)

Generation of MARTE Allocation Models from Activity Threads. - Andreas W. Liehr; Klaus J. Buchenrieder; Heike S. Rolfs; Ulrich Nageldinger (FDL (Selected Papers), 2008)

Generating MARTE Allocation Models from Activity Threads. - Andreas W. Liehr; Heike S. Rolfs; Klaus Buchenrieder; Ulrich Nageldinger (FDL, 2008)

Comprehensive Platform and Component Modeling of Heterogeneous Interconnected Systems (invited). - Jochen Zimmermann; Oliver Bringmann 001; Joachim Gerlach; Florian Schaefer; Ulrich Nageldinger (FDL, 2008)