Ulrich Rückert

According to our database1, Ulrich Rückert authored at least 165 papers between 1984 and 2019.

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2019
FPGA-Based Vision Processing System for Automatic Online Player Tracking in Indoor Sports.
Signal Processing Systems, 2019

Numerical and Experimental Evaluation of Error Estimation for Two-Way Ranging Methods.
Sensors, 2019

Towards an SSVEP-BCI Controlled Smart Home.
Proceedings of the 2019 IEEE International Conference on Systems, Man and Cybernetics, 2019

Constraint Exploration of Convolutional Network Architectures with Neuroevolution.
Proceedings of the Advances in Computational Intelligence, 2019

A Bidirectional Object Tracking and Navigation System using a True-Range Multilateration Method.
Proceedings of the 2019 International Conference on Indoor Positioning and Indoor Navigation, 2019

Multi-Modal Generative Models for Learning Epistemic Active Sensing.
Proceedings of the International Conference on Robotics and Automation, 2019

Fiducial Marker based Extrinsic Camera Calibration for a Robot Benchmarking Platform.
Proceedings of the 2019 European Conference on Mobile Robots, 2019

2018
CoreVA-MPSoC: A Many-Core Architecture with Tightly Coupled Shared and Local Data Memories.
IEEE Trans. Parallel Distrib. Syst., 2018

Multi-Modal Detection and Mapping of Static and Dynamic Obstacles in Agriculture for Process Evaluation.
Front. Robotics and AI, 2018

Coordinated Heterogeneous Distributed Perception based on Latent Space Representation.
CoRR, 2018

Towards Inverse Sensor Mapping in Agriculture.
CoRR, 2018

Development of Energy Models for Design Space Exploration of Embedded Many-Core Systems.
CoRR, 2018

AMiRo: A Mini Robot as Versatile Teaching Platform.
Proceedings of the Robotics in Education, 2018

An Analytical Study of Time of Flight Error Estimation in Two-Way Ranging Methods.
Proceedings of the 2018 International Conference on Indoor Positioning and Indoor Navigation, 2018

Generic Architecture for Modular Real-time Systems in Robotics.
Proceedings of the 15th International Conference on Informatics in Control, 2018

Resource-efficient Reconfigurable Computer-on-Module for Embedded Vision Applications.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
FPGA-based multi-robot tracking.
J. Parallel Distributed Comput., 2017

Binary Associative Memories as a Benchmark for Spiking Neuromorphic Hardware.
Front. Comput. Neurosci., 2017

An Adaptive Acknowledgement On-demand Protocol for Wireless Sensor Networks.
Proceedings of the 6th International Conference on Sensor Networks (SENSORNETS 2017), 2017

Comparing Synchronous, Mesochronous and Asynchronous NoCs for GALS Based MPSoCs.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

Reconfigurable vision processing system for player tracking in indoor sports.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

2016
Occupancy Grid Mapping with Highly Uncertain Range Sensors based on Inverse Particle Filters.
Proceedings of the 13th International Conference on Informatics in Control, Automation and Robotics (ICINCO 2016), 2016

A software assistant for user-centric calibration of a wireless body sensor.
Proceedings of the 13th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2016

Towards a comprehensive power consumption model for wireless sensor nodes.
Proceedings of the 13th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2016

Detailed Estimation of Cognitive Workload with Reference to a Modern Working Environment.
Proceedings of the Biomedical Engineering Systems and Technologies, 2016

Fine-Grained Prediction of Cognitive Workload in a Modern Working Environment by Utilizing Short-Term Physiological Parameters.
Proceedings of the 9th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2016), 2016

2015
FPGA-based circular hough transform with graph clustering for vision-based multi-robot tracking.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Evidence Grid Based Information Fusion for Semantic Classifiers in Dynamic Sensor Networks.
Proceedings of the Machine Learning for Cyber Physical Systems, 2015

Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

AMiRo: A Mini Robot for Scientific Applications.
Proceedings of the Advances in Computational Intelligence, 2015

Evaluation of interconnect fabrics for an embedded MPSoC in 28 nm FD-SOI.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Universelle Echtzeit-Ethernet Architektur zur Integration in rekonfigurierbare Automatisierungssysteme.
Proceedings of the 45. Jahrestagung der Gesellschaft für Informatik, Informatik 2015, Informatik, Energie und Umwelt, 28. September, 2015

A 65 nm standard cell library for ultra low-power applications.
Proceedings of the European Conference on Circuit Theory and Design, 2015

Robust estimation of physical activity by adaptively fusing multiple parameters.
Proceedings of the 12th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2015

2014
CoreVA: A Configurable Resource-Efficient VLIW Processor Architecture.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

2013
A systematic approach for optimized bypass configurations for application-specific embedded processors.
ACM Trans. Embedded Comput. Syst., 2013

A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control.
J. Solid-State Circuits, 2013

A reconfigurable neuroprocessor for self-organizing feature maps.
Neurocomputing, 2013

Design-space exploration of the configurable 32 bit VLIW processor CoreVA for signal processing applications.
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013

Teletesting: Path planning experimentation and benchmarking in the Teleworkbench.
Proceedings of the 2013 European Conference on Mobile Robots, 2013

Athlete Identification using Acceleration and Electrocardiographic Measurements Recorded with a Wireless Body Sensor.
Proceedings of the BIOSIGNALS 2013, 2013

Identification of Athletes During Walking and Jogging Based on Gait and Electrocardiographic Patterns.
Proceedings of the Biomedical Engineering Systems and Technologies, 2013

2012
Optimizing inter-FPGA communication by automatic channel adaptation.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

A 200mV 32b subthreshold processor with adaptive supply voltage control.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A TCMS-based architecture for GALS NoCs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Parallel neural hardware: the time is right.
Proceedings of the 20th European Symposium on Artificial Neural Networks, 2012

gNBXe - a Reconfigurable Neuroprocessor for Various Types of Self-Organizing Maps.
Proceedings of the 20th European Symposium on Artificial Neural Networks, 2012

Hardware accelerated real time classification of hyperspectral imaging data for coffee sorting.
Proceedings of the 20th European Symposium on Artificial Neural Networks, 2012

A scalable platform for run-time reconfigurable satellite payload processing.
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

Scalable and flexible vision-based multi-robot tracking system.
Proceedings of the 2012 IEEE International Symposium on Intelligent Control, 2012

2011
Design Optimizations for Tiled Partially Reconfigurable Systems.
IEEE Trans. VLSI Syst., 2011

Applying dynamic reconfiguration in the mobile robotics domain: A case study on computer vision algorithms.
TRETS, 2011

Synchronous Demodulation of Coherent 16-QAM with Feedforward Carrier Recovery.
IEICE Transactions, 2011

Integrated circuit optimization by means of evolutionary multi-objective optimization.
Proceedings of the 13th Annual Genetic and Evolutionary Computation Conference, 2011

Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

Teleworkbench: validating robot programs from simulation to prototyping with minirobots.
Proceedings of the 10th International Conference on Autonomous Agents and Multiagent Systems (AAMAS 2011), 2011

2010
Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis.
TRETS, 2010

A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror.
IEEE Trans. on Circuits and Systems, 2010

Design Space Exploration for Memory Subsystems of VLIW Architectures.
Proceedings of the Fifth International Conference on Networking, Architecture, and Storage, 2010

A Framework for the Design Space Exploration of Software-Defined Radio Applications.
Proceedings of the Mobile Lightweight Wireless Systems, 2010

High level specification of embedded listeners for monitoring of Network-on-Chips.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Multiobjective optimization for transistor sizing sub-threshold CMOS logic standard cells.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Design of 9T SRAM for dynamic voltage supplies by a multiobjective optimization approach.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
Run-time reconfigurability in embedded multiprocessors.
SIGARCH Computer Architecture News, 2009

Effect of global position information in unknown world exploration - A case study using the Teleworkbench.
Robotics Auton. Syst., 2009

A Synchronization Method for Register Traces of Pipelined Processors.
Proceedings of the Analysis, 2009

UMAC - A Universal MAC architecture for heterogeneous home networks.
Proceedings of the International Conference on Ultra Modern Telecommunications, 2009

Template matching based tracking of players in indoor team sports.
Proceedings of the Third ACM/IEEE International Conference on Distributed Smart Cameras, 2009

AMiRESot - A New Robot Soccer League with Autonomous Miniature Robots.
Proceedings of the Progress in Robotics, 2009

Ad-Hoc Communication and Localization System for Mobile Robots.
Proceedings of the Advances in Robotics, 2009

BeBot: A Modular Mobile Miniature Robot Platform Supporting Hardware Reconfiguration and Multi-standard Communication.
Proceedings of the Progress in Robotics, 2009

Topology Control in Large-Scale High Dynamic Mobile Ad-Hoc Networks.
Proceedings of the Advances in Robotics, 2009

Vision Module for Mini-robots Providing Optical Flow Processing for Obstacle Avoidance.
Proceedings of the Advances in Robotics, 2009

Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

2008
A Modified Multiple Depth First Search Algorithm for Grid Mapping Using Mini-Robots Khepera.
JCSE, 2008

A biologically-inspired and resource-efficient vision system using mobile mini-robots for obstacle avoidance.
Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2008

Robot Localization based on Visual Landmarks.
Proceedings of the ICINCO 2008, 2008

Modified Local Navigation Strategy for Unknown Environment Exploration.
Proceedings of the ICINCO 2008, 2008

An automated platform for minirobots experiments.
Proceedings of the 10th International Conference on Control, 2008

2007
Characterization of Analog Local Cluster Neural Network Hardware for Control.
IEEE Trans. Neural Networks, 2007

Resource efficiency of the GigaNetIC chip multiprocessor architecture.
Journal of Systems Architecture, 2007

Robustness of radial basis functions.
Neurocomputing, 2007

IAF Neuron Implementation for Mixed-Signal PCNN Hardware.
Proceedings of the Computational and Ambient Intelligence, 2007

Neural Inspired Architectures for Nanoelectronics.
Proceedings of the Computational and Ambient Intelligence, 2007

Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

A Control Approach to a Biophysical Neuron Model.
Proceedings of the Artificial Neural Networks, 2007

Impact of Shrinking Technologies on the Activation Function of Neurons.
Proceedings of the Artificial Neural Networks, 2007

A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation.
Proceedings of the 7th International Conference on Hybrid Intelligent Systems (HIS 2007), 2007

Controlling complexity of RBF networks by similarity.
Proceedings of the ESANN 2007, 2007

GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

A Multiprocessor Cache for Massively Parallel SoC Architectures.
Proceedings of the Architecture of Computing Systems, 2007

Teleworkbench: A Remotely-Accessible Robotic Laboratory for Education.
Proceedings of the Robots and Robot Venues: Resources for AI Education, 2007

2006
Bio-inspired massively parallel architectures for nanotechnologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Enhancing Fault Tolerance of Radial Basis Functions.
Proceedings of the International Joint Conference on Neural Networks, 2006

SIRENS: A Simple Reconfigurable Neural Hardware Structure for artificial neural network implementations.
Proceedings of the International Joint Conference on Neural Networks, 2006

Teleworkbench: An Analysis Tool for Multi-Robotic Experiments.
Proceedings of the Biologically Inspired Cooperative Computing, 2006

Pareto-optimal Noise and Approximation Properties of RBF Networks.
Proceedings of the Artificial Neural Networks, 2006

Robust Local Cluster Neural Networks.
Proceedings of the ESANN 2006, 2006

GigaNetIC - A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications.
Proceedings of the Architecture of Computing Systems, 2006

2005
A system approach for partially reconfigurable architectures.
IJES, 2005

Defragmentation Algorithms for Partially Reconfigurable Hardware.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Fault-tolerance of basis function networks using tensor product stabilizers.
Proceedings of the IEEE International Conference on Systems, 2005

A low complexity directional scheme for mobile ad hoc networks.
Proceedings of the IEEE 16th International Symposium on Personal, 2005

Analog VLSI Implementation of Adaptive Synapses in Pulsed Neural Networks.
Proceedings of the Computational Intelligence and Bioinspired Systems, 2005

Explorative Data Analysis Based on Self-organizing Maps and Automatic Map Analysis.
Proceedings of the Computational Intelligence and Bioinspired Systems, 2005

A Scalable Parallel SoC Architecture for Network Processors.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

CSD: cell-based service discovery in large-scale robot networks.
Proceedings of the 2005 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2005

Placement-Oriented Modeling of Partially Reconfigurable Architectures.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Adaptable Switch Boxes as On-Chip Routing Nodes for Networks-on-Chip.
Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005

Low-cost Bluetooth Communication for the Autonomous Mobile Minirobot Khepera.
Proceedings of the 2005 IEEE International Conference on Robotics and Automation, 2005

Tolerance of Radial Basis Functions Against Stuck-At-Faults.
Proceedings of the Artificial Neural Networks: Formal Models and Their Applications, 2005

Analytical approach to massively parallel architectures for nanotechnologies.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

Teleworkbench: A Teleoperated Platform for Multi-Robot Experiments.
Proceedings of the 3rd International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE 2005), 2005

Teleoperation of a Mobile Autonomous Robot using Web Services.
Proceedings of the 3rd International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE 2005), 2005

Universal FPGA-Microcontroller Module for Autonomous Minirobots.
Proceedings of the 3rd International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE 2005), 2005

Increasing the Resource-Efficiency of the CSMA/CA Protocol in Directional Ad Hoc Networks.
Proceedings of the Ad-Hoc, Mobile, and Wireless Networks, 4th International Conference, 2005

2004
Dynamic Reconfiguration of Real-Time Network Interfaces.
Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

Network Application Driven Instruction Set Extensions for Embedded Processing Clusters.
Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

Hardware Accelerated Data Analysis.
Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

V: Drive - Costs and Benefits of an Out-of-Band Storage Virtualization System.
Proceedings of the 21st IEEE Conference on Mass Storage Systems and Technologies / 12th NASA Goddard Conference on Mass Storage Systems and Technologies, 2004

System-on-Programmable-Chip Approach Enabling Online Fine-Grained 1D-Placement.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Distributed Path Selection (DPS) A Traf.c Engineering Protocol for IP-Networks.
Proceedings of the 37th Hawaii International Conference on System Sciences (HICSS-37 2004), 2004

gNBX - reconfigurable hardware acceleration of self-organizing maps.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Study on column wise design compaction for reconfigurable systems.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures.
Proceedings of the Field Programmable Logic and Application, 2004

A Comparative Study on System Approaches for Partially Reconfigurable Architectures.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoC.
Proceedings of the 2004 Design, 2004

Leistungsbewertung unterschiedlicher Einbettungsvariaten dynamisch rekonfigurierbarer Hardware.
Proceedings of the ARCS 2004, 2004

2003
A massively parallel architecture for self-organizing feature maps.
IEEE Trans. Neural Networks, 2003

A holistic methodology for network processor design.
Proceedings of the 28th Annual IEEE Conference on Local Computer Networks (LCN 2003), 2003

A performance evaluation method for optimizing embedded applications.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

2002
ULSI Architectures for Artificial Neural Networks.
IEEE Micro, 2002

Simulation of spiking neural networks -- architectures and implementations.
Neurocomputing, 2002

Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator.
Proceedings of the 10th Euromicro Workshop on Parallel, 2002

Dynamically Reconfigurable System-on-Programmable-Chip.
Proceedings of the 10th Euromicro Workshop on Parallel, 2002

Continuous Sonar Sensing for Mobile Mini-Robots.
Proceedings of the 2002 IEEE International Conference on Robotics and Automation, 2002

A Direction Sensitive Network Based on a Biophysical Neurone Model.
Proceedings of the Artificial Neural Networks, 2002

Dynamically Reconfigurable Hardware - A New Perspective for Neural Network Implementations.
Proceedings of the Field-Programmable Logic and Applications, 2002

A reconfigurable SOM hardware accelerator.
Proceedings of the ESANN 2002, 2002

2001
Content-Based Information Retrieval Using an Embedded Neural Associative Memory.
Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001

A methodology for behaviour design of autonomous systems.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2001

2000
Using a Dynamically Reconfigurable System to Accelerate Octree Based 3D Graphics.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

A Bootstrapping Method for Autonomous and in Site Learning of Generic Navigation Behavior.
Proceedings of the 15th International Conference on Pattern Recognition, 2000

A Rapid Prototyping Environment for Microprocessor Based System-on-Chips and Its Application to the Development of a Network Processor.
Proceedings of the Field-Programmable Logic and Applications, 2000

1999
A Visualization Tool for the Mini-Robot Khepera: Behavior Analysis and Optimization.
Proceedings of the Advances in Artificial Life, 5th European Conference, 1999

1998
Local cluster neural net analog VLSI design.
Neurocomputing, 1998

SOM accelerator system.
Neurocomputing, 1998

1997
A High Performance SOFM Hardware-System.
Proceedings of the Biological and Artificial Computation: From Neuroscience to Technology, 1997

HiBRIC-MEM, a Memory Controller for PowerPC Based Systems.
Proceedings of the 23rd EUROMICRO Conference '97, 1997

The Dynamical Nightwatch's Problem Solved by the Autonomous Micro-Robot Khepera.
Proceedings of the Artificial Evolution, Third European Conference, 1997

1995
Neural networks-extraordinary variation.
IEEE Micro, 1995

A VLSI friendly neural network with localised transfer functions.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

1993
Acceleratorboard for neural associative memories.
Neurocomputing, 1993

Hardware Design for Self-Organizing Feature Maps with Binary Input Vectors.
Proceedings of the New Trends in Neural Computation, 1993

1991
Wissensverarbeitung in neuronaler Architektur.
Proceedings of the Verteilte Künstliche Intelligenz und kooperatives Arbeiten, 1991

Application and Implementation of Neural Networks in Microelectronics.
Proceedings of the Artificial Neural Networks, 1991

1990
VLSI Implementation of an Associative Memory Based on Distributed Storage of Information.
Proceedings of the Neural Networks, 1990

1989
Integrationsgerechte Umsetzung von assoziativen Netzwerken mit verteilter Speicherung.
PhD thesis, 1989

VLSI technologies for artificial neural networks.
IEEE Micro, 1989

Selbstorganisierende Parameterkarten zur Prozeßüberwachung und -voraussage.
Proceedings of the Wissensbasierte Systeme, 1989

1986
Adaptive Associate Systems for VLSI.
Proceedings of the WOPPLOT 86, 1986

1984
Intelligent memories in VLSI.
Inf. Sci., 1984


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