Automatic verilog code generation through grammatical evolution. - Ulya R. Karpuzcu (GECCO Workshops, 2005)

Blueshift: Designing processors for timing speculation from the ground up. - Brian Greskamp; Lu Wan; Ulya R. Karpuzcu; Jeffrey J. Cook; Josep Torrellas; Deming Chen; Craig B. Zilles (HPCA, 2009)

Accurate microarchitecture-level fault modeling for studying hardware faults. - Man-Lap Li; Pradeep Ramachandran; Ulya R. Karpuzcu; Siva Kumar Sastry Hari; Sarita V. Adve (HPCA, 2009)

The BubbleWrap many-core: popping cores for sequential acceleration. - Ulya R. Karpuzcu; Brian Greskamp; Josep Torrellas (MICRO, 2009)

LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicores. - Brian Greskamp; Ulya R. Karpuzcu; Josep Torrellas (HPCA, 2010)

VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages. - Ulya R. Karpuzcu; Krishna B. Kolluru; Nam Sung Kim; Josep Torrellas (DSN, 2012)

Novel many-core architectures for energy-efficiency - Ulya R. Karpuzcu (2012)

EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing. - Ulya R. Karpuzcu; Abhishek A. Sinkar; Nam Sung Kim; Josep Torrellas (HPCA, 2013)

Coping with Parametric Variation at Near-Threshold Voltages. - Ulya R. Karpuzcu; Nam Sung Kim; Josep Torrellas (IEEE Micro, 2013)

Accordion: Toward soft Near-Threshold Voltage Computing. - Ulya R. Karpuzcu; Ismail Akturk; Nam Sung Kim (HPCA, 2014)

Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors. - Abhishek A. Sinkar; Hamid Reza Ghasemi; Michael J. Schulte; Ulya R. Karpuzcu; Nam Sung Kim (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Comparison of single-ISA heterogeneous versus wide dynamic range processors for mobile applications. - Hamid Reza Ghasemi; Ulya R. Karpuzcu; Nam Sung Kim (ICCD, 2015)

Decoupled Control and Data Processing for Approximate Near-Threshold Voltage Computing. - Ismail Akturk; Nam Sung Kim; Ulya R. Karpuzcu (IEEE Micro, 2015)

VARIUS-TC: A modular architecture-level model of parametric variation for thin-channel switches. - S. Karen Khatamifard; Michael Resch 002; Nam Sung Kim; Ulya R. Karpuzcu (ICCD, 2016)

Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks. - Dimitrios Skarlatos 002; Renji Thomas; Aditya Agrawal; Shibin Qin; Robert C. N. Pilawa-Podgurski; Ulya R. Karpuzcu; Radu Teodorescu; Nam Sung Kim; Josep Torrellas (MICRO, 2016)

Accuracy Bugs: A New Class of Concurrency Bugs to Exploit Algorithmic Noise Tolerance. - Ismail Akturk; Riad Akram; Mohammad Majharul Islam; Abdullah Muzahid; Ulya R. Karpuzcu (ACM Trans. Archit. Code Optim., 2016)

System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators. - Ayan Paul; Sang Phill Park; Dinesh Somasekhar; Young Moon Kim; Nitin Borkar; Ulya R. Karpuzcu; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2016)

AMNESIAC: Amnesic Automatic Computer. - Ismail Akturk; Ulya R. Karpuzcu (ASPLOS, 2017)

ThermoGater: Thermally-Aware On-Chip Voltage Regulation. - S. Karen Khatamifard; Longfei Wang; Weize Yu; Selçuk Köse; Ulya R. Karpuzcu (ISCA, 2017)

A Non-volatile Near-Memory Read Mapping Accelerator. - S. Karen Khatamifard; Zamshed I. Chowdhury; Nakul Pande; Meisam Razaviyayn; Chris H. Kim; Ulya R. Karpuzcu (CoRR, 2017)

On Dynamic Precision Scaling. - Serif Yesil; Ismail Akturk; Ulya R. Karpuzcu (CoRR, 2017)

Trading Computation for Communication: A Taxonomy. - Ismail Akturk; Ulya R. Karpuzcu (CoRR, 2017)

Recomputation Enabled Efficient Checkpointing. - Ismail Akturk; Ulya R. Karpuzcu (CoRR, 2017)

Efficiency, Stability, and Reliability Implications of Unbalanced Current Sharing Among Distributed On-Chip Voltage Regulators. - Longfei Wang; S. Karen Khatamifard; Orhun Aras Uzun; Ulya R. Karpuzcu; Selçuk Köse (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Mitigation of NBTI induced performance degradation in on-chip digital LDOs. - Longfei Wang; S. Karen Khatamifard; Ulya R. Karpuzcu; Selçuk Köse (DATE, 2018)

Efficient In-Memory Processing Using Spintronics. - Zamshed I. Chowdhury; Jonathan D. Harms; S. Karen Khatamifard; Masoud Zabihi; Yang Lv; Andrew Lyle; Sachin S. Sapatnekar; Ulya R. Karpuzcu; Jianping Wang 006 (IEEE Comput. Archit. Lett., 2018)

On Memory System Design for Stochastic Computing. - S. Karen Khatamifard; M. Hassan Najafi; Ali Ghoreyshi; Ulya R. Karpuzcu; David J. Lilja (IEEE Comput. Archit. Lett., 2018)

A New Class of Covert Channels Exploiting Power Management Vulnerabilities. - S. Karen Khatamifard; Longfei Wang; Selçuk Köse; Ulya R. Karpuzcu (IEEE Comput. Archit. Lett., 2018)

AISC: Approximate Instruction Set Computer. - Alexandra Ferreron; Jesús Alastruey-Benedé; Darío Suárez Gracia; Ulya R. Karpuzcu (CoRR, 2018)

Exploiting Processing in Non-Volatile Memory for Binary Neural Network Accelerators. - Salonik Resch; S. Karen Khatamifard; Zamshed Iqbal Chowdhury; Masoud Zabihi; Zhengyang Zhao 001; Jianping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (CoRR, 2018)

Computational RAM to Accelerate String Matching at Scale. - Zamshed I. Chowdhury; S. Karen Khatamifard; Zhengyang Zhao 001; Masoud Zabihi; Salonik Resch; Meisam Razaviyayn; Jianping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (CoRR, 2018)

Approximate Communication: Techniques for Reducing Communication Bottlenecks in Large-Scale Parallel Systems. - Filipe Betzel; S. Karen Khatamifard; Harini Suresh; David J. Lilja; John Sartori; Ulya R. Karpuzcu (ACM Comput. Surv., 2018)

Toward Dynamic Precision Scaling. - Serif Yesil; Ismail Akturk; Ulya R. Karpuzcu (IEEE Micro, 2018)

On Approximate Speculative Lock Elision. - S. Karen Khatamifard; Ismail Akturk; Ulya R. Karpuzcu (IEEE Trans. Multi Scale Comput. Syst., 2018)

Approximate Ultra-Low Voltage Many-Core Processor Design. - Nam Sung Kim; Ulya R. Karpuzcu (Approximate Circuits, 2019)

True In-memory Computing with the CRAM: From Technology to Applications. - Masoud Zabihi; Zhengyang Zhao 001; Zamshed I. Chowdhury; Salonik Resch; Mahendra DC; Thomas Peterson; Ulya R. Karpuzcu; Jianping Wang 006; Sachin S. Sapatnekar (ACM Great Lakes Symposium on VLSI, 2019)

POWERT Channels: A Novel Class of Covert CommunicationExploiting Power Management Vulnerabilities. - S. Karen Khatamifard; Longfei Wang; Amitabh Das; Selçuk Köse; Ulya R. Karpuzcu (HPCA, 2019)

Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis. - Zamshed I. Chowdhury; S. Karen Khatamifard; Zhaoyong Zheng; Tali Moreshet; R. Iris Bahar; Ulya R. Karpuzcu (IISWC, 2019)

Using Spin-Hall MTJs to Build an Energy-Efficient In-memory Computation Platform. - Masoud Zabihi; Zhengyang Zhao 001; D. C. Mahendra; Zamshed I. Chowdhury; Salonik Resch; Thomas Peterson; Ulya R. Karpuzcu; Jianping Wang 006; Sachin S. Sapatnekar (ISQED, 2019)

Special Session: Does Approximation Make Testing Harder (or Easier)? - R. Iris Bahar; Ulya R. Karpuzcu; Sasa Misailovic (VTS, 2019)

A Machine Learning Accelerator In-Memory for Energy Harvesting. - Salonik Resch; S. Karen Khatamifard; Zamshed Iqbal Chowdhury; Masoud Zabihi; Zhengyang Zhao 001; Jianping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (CoRR, 2019)

In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping. - Masoud Zabihi; Zamshed Iqbal Chowdhury; Zhengyang Zhao 001; Ulya R. Karpuzcu; Jianping Wang 006; Sachin S. Sapatnekar (IEEE Trans. Computers, 2019)

Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation. - Longfei Wang; S. Karen Khatamifard; Ulya R. Karpuzcu; Selçuk Köse (IEEE Trans. Very Large Scale Integr. Syst., 2019)

CRAFFT: High Resolution FFT Accelerator In Spintronic Computational RAM. - M. Hüsrev Cilasun; Salonik Resch; Zamshed Iqbal Chowdhury; Erin Olson; Masoud Zabihi; Zhengyang Zhao 001; Thomas Peterson; Jianping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (DAC, 2020)

ACR: Amnesic Checkpointing and Recovery. - Ismail Akturk; Ulya R. Karpuzcu (HPCA, 2020)

MOUSE: Inference In Non-volatile Memory for Energy Harvesting Applications. - Salonik Resch; S. Karen Khatamifard; Zamshed I. Chowdhury; Masoud Zabihi; Zhengyang Zhao 001; M. Hüsrev Cilasun; Jianping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (MICRO, 2020)

Voltage Noise Mitigation With Barrier Approximation. - Zamshed I. Chowdhury; S. Karen Khatamifard; Zhaoyong Zheng; Tali Moreshet; R. Iris Bahar; Ulya R. Karpuzcu (IEEE Comput. Archit. Lett., 2020)

Dual-precision fixed-point arithmetic for low-power ray-triangle intersections. - Krishna Rajan; Soheil Hashemi; Ulya R. Karpuzcu; Michael C. Doggett; Sherief Reda (Comput. Graph., 2020)

An Inference and Learning Engine for Spiking Neural Networks in Computational RAM (CRAM). - M. Hüsrev Cilasun; Salonik Resch; Zamshed I. Chowdhury; Erin Olson; Masoud Zabihi; Zhengyang Zhao 001; Thomas Peterson; Keshab K. Parhi; Jianping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (CoRR, 2020)

PIMBALL: Binary Neural Networks in Spintronic Memory. - Salonik Resch; S. Karen Khatamifard; Zamshed Iqbal Chowdhury; Masoud Zabihi; Zhengyang Zhao 001; Jianping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (ACM Trans. Archit. Code Optim., 2020)

CAMeleon: Reconfigurable B(T)CAM in Computational RAM. - Zamshed I. Chowdhury; Salonik Resch; M. Hüsrev Cilasun; Zhengyang Zhao 001; Masoud Zabihi; Sachin S. Sapatnekar; Jianping Wang 006; Ulya R. Karpuzcu (ACM Great Lakes Symposium on VLSI, 2021)

Seeds of SEED: H-CRAM: In-memory Homomorphic Search Accelerator using Spintronic Computational RAM. - M. Hüsrev Cilasun; Salonik Resch; Zamshed I. Chowdhury; Masoud Zabihi; Zhengyang Zhao 001; Thomas Peterson; Jian-Ping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (SEED, 2021)

Do Not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation. - Christos Sakalis; Zamshed I. Chowdhury; Shayne Wadle; Ismail Akturk; Alberto Ros 001; Magnus Själander; Stefanos Kaxiras; Ulya R. Karpuzcu (SEED, 2021)

Cryogenic PIM: Challenges & Opportunities. - Salonik Resch; M. Hüsrev Cilasun; Ulya R. Karpuzcu (IEEE Comput. Archit. Lett., 2021)

A Day In the Life of a Quantum Error. - Salonik Resch; Swamit S. Tannu; Ulya R. Karpuzcu; Moinuddin K. Qureshi (IEEE Comput. Archit. Lett., 2021)

On Value Recomputation to Accelerate Invisible Speculation. - Christos Sakalis; Zamshed I. Chowdhury; Shayne Wadle; Ismail Akturk; Alberto Ros 001; Magnus Själander; Stefanos Kaxiras; Ulya R. Karpuzcu (CoRR, 2021)

Exploring the Feasibility of Using 3D XPoint as an In-Memory Computing Accelerator. - Masoud Zabihi; Salonik Resch; M. Hüsrev Cilasun; Zamshed I. Chowdhury; Zhengyang Zhao 001; Ulya R. Karpuzcu; Jianping Wang 006; Sachin S. Sapatnekar (CoRR, 2021)

Towards Homomorphic Inference Beyond the Edge. - Salonik Resch; Zamshed I. Chowdhury; M. Hüsrev Cilasun; Masoud Zabihi; Zhengyang Zhao 001; Jian-Ping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (CoRR, 2021)

Special Issue on Quantum Computing. - Ulya R. Karpuzcu (IEEE Micro, 2021)

Spiking Neural Networks in Spintronic Computational RAM. - M. Hüsrev Cilasun; Salonik Resch; Zamshed I. Chowdhury; Erin Olson; Masoud Zabihi; Zhengyang Zhao 001; Thomas Peterson; Keshab K. Parhi; Jianping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (ACM Trans. Archit. Code Optim., 2021)

Trading Computation for Communication: A Taxonomy of Data Recomputation Techniques. - Ismail Akturk; Ulya R. Karpuzcu (IEEE Trans. Emerg. Top. Comput., 2021)

On Variable Strength Quantum ECC. - Salonik Resch; Ulya R. Karpuzcu (IEEE Comput. Archit. Lett., 2022)

Error Detection and Correction for Processing in Memory (PiM). - M. Hüsrev Cilasun; Salonik Resch; Zamshed I. Chowdhury; Masoud Zabihi; Yang Lv; Brandon Zink; Jianping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (CoRR, 2022)

Benchmarking Quantum Computers and the Impact of Quantum Noise. - Salonik Resch; Ulya R. Karpuzcu (ACM Comput. Surv., 2022)

GeNVoM: Read Mapping Near Non-Volatile Memory. - S. Karen Khatamifard; Zamshed I. Chowdhury; Nakul Pande; Meisam Razaviyayn; Chris H. Kim; Ulya R. Karpuzcu (IEEE ACM Trans. Comput. Biol. Bioinform., 2022)

CRAM-Seq: Accelerating RNA-Seq Abundance Quantification Using Computational RAM. - Zamshed I. Chowdhury; S. Karen Khatamifard; Salonik Resch; M. Hüsrev Cilasun; Zhengyang Zhao 001; Masoud Zabihi; Meisam Razaviyayn; Jian-Ping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (IEEE Trans. Emerg. Top. Comput., 2022)

Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions. - Salonik Resch; S. Karen Khatamifard; Zamshed I. Chowdhury; Masoud Zabihi; Zhengyang Zhao 001; M. Hüsrev Cilasun; Jianping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (ACM Trans. Embed. Comput. Syst., 2022)

PimCity: A Compute in Memory Substrate featuring both Row and Column Parallel Computing. - Salonik Resch; Hüsrev Cilasun; Masoud Zabihi; Zamshed Iqbal Chowdhury; Zhengyang Zhao 001; Jian-Ping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (ICRC, 2023)

On Endurance of Processing in (Nonvolatile) Memory. - Salonik Resch; M. Hüsrev Cilasun; Zamshed I. Chowdhury; Masoud Zabihi; Zhengyang Zhao 001; Jian-Ping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (ISCA, 2023)

3SAT on an All-to-All-Connected CMOS Ising Solver Chip. - M. Hüsrev Cilasun; Ziqing Zeng; Ramprasath S 001; Abhimanyu Kumar; Hao Lo; William Cho; Chris H. Kim; Ulya R. Karpuzcu; Sachin S. Sapatnekar (CoRR, 2023)

On Gate Flip Errors in Computing-In-Memory. - Zamshed I. Chowdhury; Hüsrev Cilasun; Salonik Resch; Masoud Zabihi; Yang Lv; Brandon Zink; Jian-Ping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (DATE, 2024)

On Error Correction for Nonvolatile Processing-In-Memory. - Hüsrev Cilasun; Salonik Resch; Zamshed I. Chowdhury; Masoud Zabihi; Yang Lv; Brandon Zink; Jianping Wang 006; Sachin S. Sapatnekar; Ulya R. Karpuzcu (ISCA, 2024)

On Heterogeneous Ising Machines. - Hüsrev Cilasun; Abhimanyu Kumar; Ziqing Zeng; Nafisa Sadaf Prova; Sachin S. Sapatnekar; Ulya R. Karpuzcu (CoRR, 2024)

COBI: A Coupled Oscillator Based Ising Chip for Combinatorial Optimization. - Hüsrev Cilasun; William Moy; Ziqing Zeng; Tahmida Islam; Hao Lo; Alex Vanasse; Megan Tan; Mohammad Anees; Ramprasath S 001; Abhimanyu Kumar; Sachin S. Sapatnekar; Chris H. Kim; et al. (Zenodo, 2024)

DROID: Discrete-Time Simulation for Ring-Oscillator-Based Ising Design. - Abhimanyu Kumar; S. Ramprasath 001; Chris H. Kim; Ulya R. Karpuzcu; Sachin S. Sapatnekar (CoRR, 2025)