FPGA-based design of a self-checking TMR voter. - Umar Afzaal; Jeong-A Lee (FPL, 2017)

Effect of FPGA Circuit Implementation on Error Detection Using Logic Implication Checking. - Umar Afzaal; Abdus Sami Hassan; Tooba Arifeen; Jeong-A Lee (DSD, 2018)

High-Speed Configuration Strategy for Configurable Logic Block-Based TCAM Architecture on FPGA. - Inayat Ullah; Umar Afzaal; Zahid Ullah 001; Jeong-A Lee (DSD, 2018)

DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates. - Inayat Ullah; Zahid Ullah 001; Umar Afzaal; Jeong-A Lee (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Trading the Reliability of Approximate TMR in FPGAs with the Cost of Mitigation. - Umar Afzaal; Jeong-A Lee (DSD, 2020)

Low-cost Hardware Redundancy for Fault-mitigation in Power-constrained IoT Systems. - Umar Afzaal; Jeong-A Lee (ICTC, 2020)

Improved error detection performance of logic implication checking in FPGA circuits. - Umar Afzaal; Abdus Sami Hassan; Jeong-A Lee (Microprocess. Microsystems, 2020)

Multisource Clock Tree Synthesis Through Sink Clustering and Fast Clock Latency Prediction. - Byungho Choi; Yonghwi Kwon 002; Umar Afzaal; Youngsoo Shin (ISCAS, 2023)

On the Evolutionary Synthesis of Fault-Resilient Digital Circuits. - Umar Afzaal; Abdus Sami Hassan; Muhammad Usman; Jeong-A Lee (IEEE Trans. Evol. Comput., 2023)

An Island Style Multi-Objective Evolutionary Framework for Synthesis of Memristor-Aided Logic. - Umar Afzaal; Seunggyu Lee; Youngsoo Shin (ASP-DAC, 2025)