Contactless VLSI Laser Probing. - Uming Ko; Dinesh G. Patel; Francois J. Henley (ITC, 1985)

Energy optimization of multi-level processor cache architectures. - Uming Ko; Poras T. Balsara; Ashwini K. Nanda (ISLPD, 1995)

Short-circuit power driven gate sizing technique for reducing power dissipation. - Uming Ko; Poras T. Balsara (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Low-power design techniques for high-performance CMOS adders. - Uming Ko; T. Balsara; Wai Lee (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Design techniques for high performance, energy efficient control logic. - Uming Ko; Anthony M. Hill; Poras T. Balsara (ISLPED, 1996)

A Repeater Optimization Methodology for Deep Sub-Micron, High Performance Processors. - David Li; Andrew Pua; Pranjal Srivastava; Uming Ko (ICCD, 1997)

High-performance, low-power design techniques for dynamic to static logic interface. - June Jiang; Kan Lu; Uming Ko (ISLPED, 1997)

Hybrid dual-threshold design techniques for high-performance processors with low-power features. - Uming Ko; Andrew Pua; Anthony M. Hill; Pranjal Srivastava (ISLPED, 1997)

Energy optimization of multilevel cache architectures for RISC and CISC processors. - Uming Ko; Poras T. Balsara; Ashwini K. Nanda (IEEE Trans. Very Large Scale Integr. Syst., 1998)

DSP for the Third Generation Wireless Communications. - Uming Ko; Mike McMahan; Edgar Auslander (ICCD, 1999)

High-performance energy-efficient D-flip-flop circuits. - Uming Ko; Poras T. Balsara (IEEE Trans. Very Large Scale Integr. Syst., 2000)

A design platform for 90-nm leakage reduction techniques. - Philippe Royannez; Hugh Mair; Franck Dahan; Mike Wagner; Mark Streeter; Laurent Bouetel; Joel Blasquez; H. Clasen; G. Semino; Julie Dong; D. Scott; B. Pitts; et al. (DAC, 2005)

Entering the hot zone - can you handle the heat and be cool? - Andrew Yang; Rajit Chandra; Simon Burke; Javier A. DeLaCruz; Sribalan Santhanam; Uming Ko (DAC, 2006)

Solutions for logic and processor core design at the 45nm technology node & and below. - Philippe Royannez; Hugh Mair; Michael Clinton; Uming Ko (ICECS, 2007)

A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques. - Gordon Gammie; Alice Wang; Minh Chau; Sumanth Gururajarao; Robert Pitts; Fabien Jumel; Stacey Engel; Philippe Royannez; Rolf Lagerquist; Hugh Mair; Jeff Vaccani; Greg Baldwin; et al. (ISSCC, 2008)

SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors. - Gordon Gammie; Alice Wang; Hugh Mair; Rolf Lagerquist; Minh Chau; Philippe Royannez; Sumanth Gururajarao; Uming Ko (Proc. IEEE, 2010)

A 28nm 0.6V low-power DSP for mobile applications. - Gordon Gammie; Nathan Ickes; Mahmut E. Sinangil; Rahul Rithe; Jie Gu 007; Alice Wang; Hugh Mair; Satyendra Datla; Bing Rong; Sushma Honnavara Prasad; Lam Ho; Greg Baldwin; et al. (ISSCC, 2011)

Ultra-low power challenges for the next generation ASIC. - Uming Ko (ISLPED, 2012)

A 28 nm 0.6 V Low Power DSP for Mobile Applications. - Nathan Ickes; Gordon Gammie; Mahmut E. Sinangil; Rahul Rithe; Jie Gu 007; Alice Wang; Hugh Mair; Satyendra Datla; Bing Rong; Sushma Honnavara Prasad; Lam Ho; Greg Baldwin; et al. (IEEE J. Solid State Circuits, 2012)

EP3: Empowering the killer SoC applications of 2020. - Shekhar Borkar; Uming Ko; Ali Keshavarzi; Eugenio Cantatore (ISSCC, 2013)

Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference. - Maurits Ortmanns; Timothy C. Fischer; Uming Ko; Wim Dehaene; Yasuhiro Takai (IEEE J. Solid State Circuits, 2013)

10.3 heterogeneous multi-processing quad-core CPU and dual-GPU design for optimal performance, power, and thermal tradeoffs in a 28nm mobile application processor. - Alice Wang; Tsung-Yao Lin; Shichin Ouyang; Wei-Hung Huang; Jidong Wang; Shu-Hsin Chang; Sheng-Ping Chen; Chun-Hsiung Hu; J. C. Tai; Koan-Sin Tan; Meng-Nan Tsou; Ming-Hsien Lee; et al. (ISSCC, 2014)

23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques. - Hugh Mair; Gordon Gammie; Alice Wang; Sumanth Gururajarao; Ichiro Lin; HsinChen Chen; Wuan Kuo; Anand Rajagopalan; Wei-Zheng Ge; Rolf Lagerquist; Syed Rahman; C. J. Chung; et al. (ISSCC, 2015)

Analog-digital partitioning and coupling in 3D-IC for RF applications. - Gilad Yahalom; Stacy Ho; Alice Wang; Uming Ko; Anantha P. Chandrakasan (3DIC, 2016)

Enabling simultaneously bi-directional TSV signaling for energy and area efficient 3D-ICs. - Sunghyun Park 002; Alice Wang; Uming Ko; Li-Shiuan Peh; Anantha P. Chandrakasan (DATE, 2016)

4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance. - Hugh Mair; Gordon Gammie; Alice Wang; Rolf Lagerquist; C. J. Chung; Sumanth Gururajarao; Ping Kao; Anand Rajagopalan; Anirban Saha; Amit Jain; Ericbill Wang; Shichin Ouyang; et al. (ISSCC, 2016)

3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance. - Hugh Mair; Ericbill Wang; Alice Wang; Ping Kao; Yuwen Tsai; Sumanth Gururajarao; Rolf Lagerquist; Jin Son; Gordon Gammie; Gordon Lin; Achuta Thippana; Kent Li; et al. (ISSCC, 2017)