BatchSim: Parallel RTL Simulation Using Inter-Cycle Batching and Task Graph Parallelism. - Jie Tong; Liangliang Chang; Umit Yusuf Ogras; Tsung-Wei Huang (ISVLSI, 2024)

Scalable Code Generation for RTL Simulation of Deep Learning Accelerators With MLIR. - Jie Tong; Wan-Luan Lee; Umit Yusuf Ogras; Tsung-Wei Huang (Euro-Par (1), 2025)