Low-distortion Continuous-time R-MOSFET-C Filters. - Un-Ku Moon; Bang-Sup Song (ISCAS, 1993)

Design of a low-distortion 22-kHz fifth-order Bessel filter. - Un-Ku Moon; Bang-Sup Song (IEEE J. Solid State Circuits, 1993)

Low-voltage switched-capacitor circuits. - E. Bidari; Mustafa Keskin; Franco Maloberti; Un-Ku Moon; Jesper Steensgaard; Gabor C. Temes (ISCAS (2), 1999)

Mismatch-shaping serial digital-to-analog converter. - Jesper Steensgaard; Un-Ku Moon; Gabor C. Temes (ISCAS (2), 1999)

Capacitor mismatch error cancellation technique for a successive approximation A/D converter. - Zhiliang Zheng; Un-Ku Moon; Jesper Steensgaard; Bo Wang; Gabor C. Temes (ISCAS (2), 1999)

Digital techniques for improving the accuracy of data converters. - Un-Ku Moon; Gabor C. Temes; Jesper Steensgaard (IEEE Commun. Mag., 1999)

Improved adaptive digital compensation for cascaded ΔΣ ADCs. - Peter Kiss; José Silva 002; Un-Ku Moon; John T. Stonick; Gabor C. Temes (ISCAS, 2000)

An adaptive offset cancellation mixer for direct conversion receivers in 2.4 GHz CMOS. - Mark Lehne; John T. Stonick; Un-Ku Moon (ISCAS, 2000)

A switched-capacitor DAC with analog mismatch correction. - Un-Ku Moon; José Silva 002; Jesper Steensgaard; Gabor C. Temes (ISCAS, 2000)

Efficient common-mode feedback circuits for pseudo-differential switched-capacitor stages. - Lei Wu; Mustafa Keskin; Un-Ku Moon; Gabor C. Temes (ISCAS, 2000)

Efficient error-cancelling algorithmic ADC. - Zhilliang Zheng; Byung-Moo Min; Un-Ku Moon; Gabor C. Temes (ISCAS, 2000)

CMOS high-frequency switched-capacitor filters for telecommunication applications. - Un-Ku Moon (IEEE J. Solid State Circuits, 2000)

Correction to "CMOS high-frequency switched-capacitor filters for telecommunication applications". - Un-Ku Moon (IEEE J. Solid State Circuits, 2000)

A CMOS self-calibrating frequency synthesizer. - William B. Wilson; Un-Ku Moon; Kadaba R. Lakshmikumar; Liang Dai (IEEE J. Solid State Circuits, 2000)

A 1.8 V CMOS DAC cell with ultra high gain op-amp in 0.0143 mm2. - Brandon Greenley; Un-Ku Moon; Raymond Veith (ISCAS (1), 2001)

Low-voltage low-sensitivity switched-capacitor bandpass Sigma-Delta modulator. - Mustafa Keskin; Un-Ku Moon; Gabor C. Temes (ISCAS (1), 2001)

Multibit Sigma-Delta ADC with mixed-mode DAC error correction. - Peter Kiss; Un-Ku Moon; Jesper Steensgaard; John T. Stonick; Gabor C. Temes (ISCAS (1), 2001)

Area efficient CMOS charge pump circuits. - Ryan Perigny; Un-Ku Moon; Gabor C. Temes (ISCAS (1), 2001)

Low-voltage pipelined ADC using opamp-reset switching technique. - Dong-Young Chang; Lei Wu; Un-Ku Moon (CICC, 2002)

Digital techniques for improved ΔΣ data conversion. - José Silva 002; Xuesheng Wang; Peter Kiss; Un-Ku Moon; Gabor C. Temes (CICC, 2002)

An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 μm CMOS. - Jeff L. Sonntag; John T. Stonick; James Gorecki; Bill Beale; Bill Check; Xue-Mei Gong; Joe Guiliano; Kyong Lee; Bob Lefferts; David A. Yokoyama-Martin; Un-Ku Moon; Amber Sengir; et al. (CICC, 2002)

A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDR. - Sang-Min Yoo; Tae-Hwan Oh; Jung-Woong Moon; Seung-Hoon Lee 006; Un-Ku Moon (CICC, 2002)

High-speed pipelined A/D converter using time-shifted CDS technique. - Jipeng Li; Un-Ku Moon (ISCAS (1), 2002)

Buck-boost switched-capacitor DC-DC voltage regulator using delta-sigma control loop. - Arun Rao; William McIntyre; J. Parry; Un-Ku Moon; Gabor C. Temes (ISCAS (4), 2002)

Digital correlation technique for the estimation and correction of DAC errors in multibit mash Delta-Sigma ADCs. - X. Wang; Un-Ku Moon; M. Liu; Gabor C. Temes (ISCAS (4), 2002)

A 1-V 10-MHz clock-rate 13-bit CMOS ΔΣ modulator using unity-gain-reset op amps. - Mustafa Keskin; Un-Ku Moon; Gabor C. Temes (IEEE J. Solid State Circuits, 2002)

A two-chip interface for a MEMS accelerometer. - Tetsuya Kajita; Un-Ku Moon; Gabor C. Temes (IEEE Trans. Instrum. Meas., 2002)

A Noise-shaping Accelerometer Interface Circuit for Two-chip Implementation. - Tetsuya Kajita; Un-Ku Moon; Gabor C. Temes (VLSI Design, 2002)

A 1.8-V 67mW 10-bit 100MSPS pipelined ADC using time-shifted CDS technique. - Jipeng Li; Un-Ku Moon (CICC, 2003)

An extended radix-based digital calibration technique for multi-stage ADC. - Jipeng Li; Un-Ku Moon (ISCAS (1), 2003)

Continuous-time, frequency translating, bandpass delta-sigma modulator. - Anurag Pulincherry; Mike Hufford; Eric Naviasky; Un-Ku Moon (ISCAS (1), 2003)

A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique. - Dong-Young Chang; Un-Ku Moon (IEEE J. Solid State Circuits, 2003)

Analysis of PLL clock jitter in high-speed serial links. - Pavan Kumar Hanumolu; Bryan Casper; Randy Mooney; Gu-Yeon Wei; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

Background calibration techniques for multistage pipelined ADCs with digital redundancy. - Jipeng Li; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

A 0.8V accurately-tuned continuous-time filter. - Gowtham Vemulapalli; Pavan Kumar Hanumolu; Un-Ku Moon (CICC, 2004)

Experimental verification of a correlation-based correction algorithm for multi-bit delta-sigma ADCs. - Xuesheng Wang; Yuhua Guo; Un-Ku Moon; Gabor C. Temes (CICC, 2004)

Jitter in high-speed serial and parallel links. - Pavan Kumar Hanumolu; Bryan Casper; Randy Mooney; Gu-Yeon Wei; Un-Ku Moon (ISCAS (4), 2004)

An improved algorithmic ADC clocking scheme. - Min-Gyu Kim; Gil-Cho Ahn; Un-Ku Moon (ISCAS (1), 2004)

Low-distortion delta-sigma topologies for MASH architectures. - José B. Silva; Un-Ku Moon; Gabor C. Temes (ISCAS (1), 2004)

A tunable duty-cycle-controlled switched-R-MOSFET-C CMOS filter for low-voltage and high-linearity applications. - Shelly Xiao; José B. Silva; Un-Ku Moon; Gabor C. Temes (ISCAS (1), 2004)

A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique. - Jipeng Li; Un-Ku Moon (IEEE J. Solid State Circuits, 2004)

Radix-based digital calibration techniques for multi-stage recycling pipelined ADCs. - Dong-Young Chang; Jipeng Li; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Analysis of charge-pump phase-locked loops. - Pavan Kumar Hanumolu; Merrick Brownlee; Kartikeya Mayaram; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

CMOS implementation of nonlinear spectral-line timing recovery in digital data-communication systems. - Un-Ku Moon; Gang Huang (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Continuous-time filter design optimized for reduced die area. - Charles Myers; Brandon Greenley; Daniel Thomas; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching. - Sang-Min Yoo; Jong-Bum Park; Seung-Hoon Lee 006; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

Will continued process-node shrinks kill high-performance analog design? - Jafar Savoj; David Rich; Brett Forejt; Peter R. Kinget; Un-Ku Moon; Modest M. Oprysko; Behzad Razavi; Hisashi (Sam) Shichijo; Albert Z. Wang (CICC, 2005)

A low spur fractional-N frequency synthesizer architecture. - Volodymyr Kratyuk; Pavan Kumar Hanumolu; Un-Ku Moon; Kartikeya Mayaram (ISCAS (3), 2005)

Analysis of supply and ground noise sensitivity in ring and LC oscillators. - Volodymyr Kratyuk; Igor Vytyaz; Un-Ku Moon; Kartikeya Mayaram (ISCAS (6), 2005)

A 10-bit algorithmic A/D converter for cytosensor application. - Thirumalai Rengachari; Vivek Sharma; Gabor C. Temes; Un-Ku Moon (ISCAS (6), 2005)

A generic multilevel multiplying D/A converter for pipelined ADCs. - Vivek Sharma; Un-Ku Moon; Gabor C. Temes (ISCAS (6), 2005)

An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications. - Ting Wu 003; Pavan Kumar Hanumolu; Un-Ku Moon; Kartikeya Mayaram (ISCAS (4), 2005)

A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators. - Gil-Cho Ahn; Dong-Young Chang; Matthew E. Brown; Naoto Ozaki; Hiroshi Youra; Ken Yamamura; Koichi Hamashita; Kaoru Takasuka; Gábor C. Temes; Un-Ku Moon (IEEE J. Solid State Circuits, 2005)

A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR. - Jipeng Li; Gil-Cho Ahn; Dong-Young Chang; Un-Ku Moon (IEEE J. Solid State Circuits, 2005)

Noise-shaping techniques applied to switched-capacitor voltage regulators. - Arun Rao; William McIntyre; Un-Ku Moon; Gábor C. Temes (IEEE J. Solid State Circuits, 2005)

A 0.8-V accurately tuned linear continuous-time filter. - Gowtham Vemulapalli; Pavan Kumar Hanumolu; Youn-Jae Kook; Un-Ku Moon (IEEE J. Solid State Circuits, 2005)

Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters. - Dong-Young Chang; Gil-Cho Ahn; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A low-Voltage 10-bit CMOS DAC in 0.01-mm2 die area. - Brandon Greenley; Raymond Veith; Dong-Young Chang; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

A time-delay jitter-insensitive continuous-time bandpass ΔΣ modulator architecture. - Anurag Pulincherry; Mike Hufford; Eric Naviasky; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

A 1.6Gbps Digital Clock and Data Recovery Circuit. - Pavan Kumar Hanumolu; Min-Gyu Kim; Gu-Yeon Wei; Un-Ku Moon (CICC, 2006)

A 0.6V Highly Linear Switched-R-MOSFET-C Filter. - Peter Kurahashi; Pavan Kumar Hanumolu; Gabor C. Temes; Un-Ku Moon (CICC, 2006)

The effect of switch resistance on pipelined ADC MDAC settling time. - Josh Carnes; Un-Ku Moon (ISCAS, 2006)

Constant transconductance bias circuit with an on-chip resistor. - Nasser Talebbeydokhti; Pavan Kumar Hanumolu; Peter Kurahashi; Un-Ku Moon (ISCAS, 2006)

Dependence of LC VCO oscillation frequency on bias current. - Ting Wu 003; Un-Ku Moon; Kartikeya Mayaram (ISCAS, 2006)

A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning. - Merrick Brownlee; Pavan Kumar Hanumolu; Kartikeya Mayaram; Un-Ku Moon (ISSCC, 2006)

A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning. - Merrick Brownlee; Pavan Kumar Hanumolu; Kartikeya Mayaram; Un-Ku Moon (IEEE J. Solid State Circuits, 2006)

Comments on 'Split ADC' architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC". - Jipeng Li; Un-Ku Moon; John A. McNeill; Michael C. W. Coln; Brian J. Larivee (IEEE J. Solid State Circuits, 2006)

A 1V 10b 30MSPS Switched-RC Pipelined ADC. - Gil-Cho Ahn; Min-Gyu Kim; Pavan Kumar Hanumolu; Un-Ku Moon (CICC, 2007)

A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance. - Merrick Brownlee; Pavan Kumar Hanumolu; Un-Ku Moon (CICC, 2007)

Digitally-Enhanced Phase-Locking Circuits. - Pavan Kumar Hanumolu; Gu-Yeon Wei; Un-Ku Moon; Kartikeya Mayaram (CICC, 2007)

Low-Power and High-Speed Pipelined ADC Using Time-Aligned CDS Technique. - Youn-Jae Kook; Jipeng Li; Bumha Lee; Un-Ku Moon (CICC, 2007)

A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range. - Volodymyr Kratyuk; Pavan Kumar Hanumolu; Kartikeya Mayaram; Un-Ku Moon (CICC, 2007)

A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop. - Ting Wu 003; Pavan Kumar Hanumolu; Kartikeya Mayaram; Un-Ku Moon (CICC, 2007)

Parameter Finding Methods for Oscillators with a Specified Oscillation Frequency. - Igor Vytyaz; David C. Lee; Suihua Lu; Amit Mehrotra; Un-Ku Moon; Kartikeya Mayaram (DAC, 2007)

Design and Analysis of Noise Tolerant Ring Oscillators Using Maneatis Delay Cells. - Josh Carnes; Igor Vytyaz; Pavan Kumar Hanumolu; Kartikeya Mayaram; Un-Ku Moon (ICECS, 2007)

An Efficient Design Procedure for High-Speed Low-Power Dual-Modulus CMOS Prescalers. - Ranganathan Desikachari; Mark Steeds; Jeffrey M. Huard; Un-Ku Moon (ICECS, 2007)

State-of-the-art continuous-time filters from scratch. - Un-Ku Moon (ICECS, 2007)

Time-Shifted CDS Enhancement of Comparator-Based MDAC for Pipelined ADC Applications. - Omid Rajaee; Nima Maghari; Un-Ku Moon (ICECS, 2007)

Design Considerations for Stochastic Analog-to-Digital Conversion. - Skyler Weaver; Daniel Knierim; Roland Wazenried; Un-Ku Moon (ICECS, 2007)

Process-Independent Resistor Temperature-Coefficients using Series/Parallel and Parallel/Series Composite Resistors. - B. Robert Gregoire; Un-Ku Moon (ISCAS, 2007)

A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing Requirement. - Sunwoo Kwon; Un-Ku Moon (ISCAS, 2007)

Mixed-Order Sturdy MASH Delta-Sigma Modulator. - Nima Maghari; Sunwoo Kwon; Gabor C. Temes; Un-Ku Moon (ISCAS, 2007)

Periodic Steady-State Analysis of Oscillators with a Specified Oscillation Frequency. - Igor Vytyaz; David C. Lee; Suihua Lu; Amit Mehrotra; Un-Ku Moon; Kartikeya Mayaram (ISCAS, 2007)

Design of Low-Voltage Highly Linear Switched-R-MOSFET-C Filters. - Peter Kurahashi; Pavan Kumar Hanumolu; Gabor C. Temes; Un-Ku Moon (IEEE J. Solid State Circuits, 2007)

An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators. - Ting Wu 003; Kartikeya Mayaram; Un-Ku Moon (IEEE J. Solid State Circuits, 2007)

A Sub 1-V Constant Gm- C Switched-Capacitor Current Source. - B. Robert Gregoire; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy. - Volodymyr Kratyuk; Pavan Kumar Hanumolu; Un-Ku Moon; Kartikeya Mayaram (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A continuous-time input pipeline ADC. - David Gubbins; Bumha Lee; Pavan Kumar Hanumolu; Un-Ku Moon (CICC, 2008)

A 1V downconversion filter using duty-cycle controlled bandwidth tuning. - Peter Kurahashi; Pavan Kumar Hanumolu; Un-Ku Moon (CICC, 2008)

74dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35dB opamp gain. - Nima Maghari; Sunwoo Kwon; Un-Ku Moon (CICC, 2008)

Noise tolerant oscillator design using perturbation projection vector analysis. - Igor Vytyaz; Josh Carnes; Ting Wu 003; Pavan Kumar Hanumolu; Un-Ku Moon; Kartikeya Mayaram (CICC, 2008)

Periodic Steady-State Analysis Augmented with Design Equality Constraints. - Igor Vytyaz; Pavan Kumar Hanumolu; Un-Ku Moon; Kartikeya Mayaram (DATE, 2008)

Reducing the effects of component mismatch by using relative size information. - B. Robert Gregoire; Un-Ku Moon (ISCAS, 2008)

Multi-loop efficient sturdy MASH delta-sigma modulators. - Nima Maghari; Un-Ku Moon (ISCAS, 2008)

Enhanced multi-bit delta-sigma modulator with two-step pipeline quantizer. - Omid Rajaee; Un-Ku Moon (ISCAS, 2008)

Parameter variation analysis for voltage controlled oscillators in phase-locked loops. - Igor Vytyaz; David C. Lee; Un-Ku Moon; Kartikeya Mayaram (ISCAS, 2008)

An Over-60dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp with 30dB Loop Gain. - B. Robert Gregoire; Un-Ku Moon (ISSCC, 2008)

An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain. - B. Robert Gregoire; Un-Ku Moon (IEEE J. Solid State Circuits, 2008)

A Sub-Picosecond Resolution 0.5-1.5 GHz Digital-to-Phase Converter. - Pavan Kumar Hanumolu; Volodymyr Kratyuk; Gu-Yeon Wei; Un-Ku Moon (IEEE J. Solid State Circuits, 2008)

A Wide-Tracking Range Clock and Data Recovery Circuit. - Pavan Kumar Hanumolu; Gu-Yeon Wei; Un-Ku Moon (IEEE J. Solid State Circuits, 2008)

A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC. - Min-Gyu Kim; Gil-Cho Ahn; Pavan Kumar Hanumolu; Sanghyeon Lee; Sang-Ho Kim; Seung-Bin You; Jae-Whui Kim; Gabor C. Temes; Un-Ku Moon (IEEE J. Solid State Circuits, 2008)

Sensitivity Analysis for Oscillators. - Igor Vytyaz; David C. Lee; Pavan Kumar Hanumolu; Un-Ku Moon; Kartikeya Mayaram (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A Note From the Editors. - Gianluca Setti; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A continuous-time input pipeline ADC with inherent anti-alias filtering. - David Gubbins; Sunwoo Kwon; Bumha Lee; Pavan Kumar Hanumolu; Un-Ku Moon (CICC, 2009)

An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing. - Sunwoo Kwon; Pavan Kumar Hanumolu; Sang-Ho Kim; Sung-No Lee; Seung-Bin You; Ho-Jin Park; Jae-Whui Kim; Un-Ku Moon (CICC, 2009)

A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS. - Tawfiq Musah; Sunwoo Kwon; Hasnain Lakdawala; Krishnamurthy Soumyanath; Un-Ku Moon (CICC, 2009)

A multiplexer-based digital passive linear counter (PLINCO). - Skyler Weaver; Benjamin P. Hershberg; Pavan Kumar Hanumolu; Un-Ku Moon (ICECS, 2009)

A 10 MS/s 11-bit 0.19 mm2 Algorithmic ADC With Improved Clocking Scheme. - Min-Gyu Kim; Pavan Kumar Hanumolu; Un-Ku Moon (IEEE J. Solid State Circuits, 2009)

A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver. - Kyehyung Lee; Qingdong Meng; Tetsuro Sugimoto; Koichi Hamashita; Kaoru Takasuka; Seiji Takeuchi; Un-Ku Moon; Gabor C. Temes (IEEE J. Solid State Circuits, 2009)

74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain. - Nima Maghari; Sunwoo Kwon; Un-Ku Moon (IEEE J. Solid State Circuits, 2009)

A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback. - Naga Sasidhar; Youn-Jae Kook; Seiji Takeuchi; Koichi Hamashita; Kaoru Takasuka; Pavan Kumar Hanumolu; Un-Ku Moon (IEEE J. Solid State Circuits, 2009)

Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers. - Ting Wu 003; Pavan Kumar Hanumolu; Kartikeya Mayaram; Un-Ku Moon (IEEE J. Solid State Circuits, 2009)

Automated Design and Optimization of Low-Noise Oscillators. - Igor Vytyaz; David C. Lee; Pavan Kumar Hanumolu; Un-Ku Moon; Kartikeya Mayaram (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Guest Editorial Special Issue on ISCAS 2008. - Anthony Chan Carusone; Yehea Ismail; Un-Ku Moon; Hanspeter Schmid; Wouter A. Serdijn; Gianluca Setti (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Introducing Jump-Start Tutorials. - Anthony Chan Carusone; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A Digital PLL With a Stochastic Time-to-Digital Converter. - Volodymyr Kratyuk; Pavan Kumar Hanumolu; Kerem Ok; Un-Ku Moon; Kartikeya Mayaram (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A +5dBFS third-order extended dynamic range single-loop ΔΣ modulator. - Nima Maghari; Skyler Weaver; Un-Ku Moon (CICC, 2010)

Asynchronous CLS for Zero Crossing based Circuits. - Hariprasath Venkatram; Benjamin P. Hershberg; Un-Ku Moon (ICECS, 2010)

PDF folding for stochastic flash ADCs. - Skyler Weaver; Benjamin P. Hershberg; Un-Ku Moon (ICECS, 2010)

Precise area-controlled return-to-zero current steering DAC with reduced sensitivity to clock jitter. - Nima Maghari; Un-Ku Moon (ISCAS, 2010)

A double-sampled path-coupled single-loop ΣΔ modulator using noise-shaped integrating quantizer. - Nima Maghari; Un-Ku Moon (ISCAS, 2010)

Pseudo-differential zero-crossing-based circuit with differential error suppression. - Tawfiq Musah; Un-Ku Moon (ISCAS, 2010)

An interstage correlated double sampling technique for switched-capacitor gain stages. - Omid Rajaee; Yue Hu; Manideep Gande; Tawfiq Musah; Un-Ku Moon (ISCAS, 2010)

A 1.4V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using a 300mV output swing opamp. - Benjamin P. Hershberg; Skyler Weaver; Un-Ku Moon (ISSCC, 2010)

Continuous-Time Input Pipeline ADCs. - David Gubbins; Bumha Lee; Pavan Kumar Hanumolu; Un-Ku Moon (IEEE J. Solid State Circuits, 2010)

Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp. - Benjamin P. Hershberg; Skyler Weaver; Un-Ku Moon (IEEE J. Solid State Circuits, 2010)

An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18 μ m CMOS. - Charles T. Peach; Un-Ku Moon; David J. Allstot (IEEE J. Solid State Circuits, 2010)

Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC. - Omid Rajaee; Tawfiq Musah; Nima Maghari; Seiji Takeuchi; Mitsuru Aniya; Koichi Hamashita; Un-Ku Moon (IEEE J. Solid State Circuits, 2010)

Stochastic Flash Analog-to-Digital Conversion. - Skyler Weaver; Benjamin P. Hershberg; Peter Kurahashi; Daniel Knierim; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A 30% beyond VDD signal swing 9-ENOB pipelined ADC using a 1.2V 30dB loop-gain opamp. - B. Robert Gregoire; Tawfiq Musah; Nima Maghari; Skyler Weaver; Un-Ku Moon (A-SSCC, 2011)

A 10b Ternary SAR ADC with decision time quantization based redundancy. - Jon Guerber; Manideep Gande; Hariprasath Venkatram; Allen Waters; Un-Ku Moon (A-SSCC, 2011)

A 0.7V 810µW 10b 30MS/s comparator-based two-step pipelined ADC. - Ho-Young Lee; David Gubbins; Bumha Lee; Un-Ku Moon (CICC, 2011)

Binary Access Memory: An optimized lookup table for successive approximation applications. - Benjamin P. Hershberg; Skyler Weaver; Seiji Takeuchi; Koichi Hamashita; Un-Ku Moon (ISCAS, 2011)

A third-order DT ΔΣ modulator using noise-shaped bidirectional single-slope quantizer. - Nima Maghari; Un-Ku Moon (ISSCC, 2011)

A Third-Order DT ΔΣ Modulator Using Noise-Shaped Bi-Directional Single-Slope Quantizer. - Nima Maghari; Un-Ku Moon (IEEE J. Solid State Circuits, 2011)

Low-OSR Over-Ranging Hybrid ADC Incorporating Noise-Shaped Two-Step Quantizer. - Omid Rajaee; Seiji Takeuchi; Mitsuru Aniya; Koichi Hamashita; Un-Ku Moon (IEEE J. Solid State Circuits, 2011)

Analysis of Residue Integration Sampling With Improved Jitter Immunity. - Taehwan Oh; Nima Maghari; David Gubbins; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Design-Oriented Analysis of Circuits With Equality Constraints. - Igor Vytyaz; Pavan Kumar Hanumolu; Un-Ku Moon; Kartikeya Mayaram (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Domino-Logic-Based ADC for Digital Synthesis. - Skyler Weaver; Benjamin P. Hershberg; Nima Maghari; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Enhanced SAR ADC energy efficiency from the early reset merged capacitor switching algorithm. - Jon Guerber; Hariprasath Venkatram; Taehwan Oh; Un-Ku Moon (ISCAS, 2012)

The effect of correlated level shifting on noise performance in switched capacitor circuits. - Benjamin P. Hershberg; Tawfiq Musah; Skyler Weaver; Un-Ku Moon (ISCAS, 2012)

Correlated jitter sampling for jitter cancellation in pipelined TDC. - Taehwan Oh; Hariprasath Venkatram; Jon Guerber; Un-Ku Moon (ISCAS, 2012)

Class A+ amplifier with controlled positive feedback for discrete-time signal processing circuits. - Hariprasath Venkatram; Taehwan Oh; Jon Guerber; Un-Ku Moon (ISCAS, 2012)

A 31.3fJ/conversion-step 70.4dB SNDR 30MS/s 1.2V two-step pipelined ADC in 0.13μm CMOS. - Ho-Young Lee; Bumha Lee; Un-Ku Moon (ISSCC, 2012)

Little-known features of well-known creatures. - Un-Ku Moon; Shanthi Pavan (ISSCC, 2012)

A 71dB dynamic range third-order ΔΣ TDC using charge-pump. - Manideep Gande; Nima Maghari; Taehwan Oh; Un-Ku Moon (VLSIC, 2012)

A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers. - Benjamin P. Hershberg; Skyler Weaver; Kazuki Sobue; Seiji Takeuchi; Koichi Hamashita; Un-Ku Moon (VLSIC, 2012)

A 5MHz BW 70.7dB SNDR noise-shaped two-step quantizer based ΔΣ ADC. - Taehwan Oh; Nima Maghari; Un-Ku Moon (VLSIC, 2012)

Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques. - Pavan Kumar Hanumolu; Un-Ku Moon; Terri S. Fiez (VLSI Design, 2012)

A 10-b Ternary SAR ADC With Quantization Time Information Utilization. - Jon Guerber; Hariprasath Venkatram; Manideep Gande; Allen Waters; Un-Ku Moon (IEEE J. Solid State Circuits, 2012)

Ring Amplifiers for Switched Capacitor Circuits. - Benjamin P. Hershberg; Skyler Weaver; Kazuki Sobue; Seiji Takeuchi; Koichi Hamashita; Un-Ku Moon (IEEE J. Solid State Circuits, 2012)

New Associate Editors. - Un-Ku Moon (IEEE J. Solid State Circuits, 2012)

New Associate Editor. - Un-Ku Moon (IEEE J. Solid State Circuits, 2012)

The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping. - Jon Guerber; Manideep Gande; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Rail-to-Rail Input Pipelined ADC Incorporating Multistage Signal Mapping. - Naga Sasidhar; David Gubbins; Pavan Kumar Hanumolu; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Blind background calibration of harmonic distortion based on selective sampling. - Manideep Gande; Ho-Young Lee; Hariprasath Venkatram; Jon Guerber; Un-Ku Moon (CICC, 2013)

Parallel gain enhancement technique for switched-capacitor circuits. - Hariprasath Venkatram; Benjamin P. Hershberg; Taehwan Oh; Manideep Gande; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (CICC, 2013)

Analysis of back-end flash in a 1.5b/stage pipelined ADC. - Manideep Gande; Jon Guerber; Un-Ku Moon (ISCAS, 2013)

Message From the Outgoing Editor-in-Chief. - Un-Ku Moon (IEEE J. Solid State Circuits, 2013)

Highly Linear Noise-Shaped Pipelined ADC Utilizing a Relaxed Accuracy Front-End. - Omid Rajaee; Un-Ku Moon (IEEE J. Solid State Circuits, 2013)

Detection and Correction Methods for Single Event Effects in Analog to Digital Converters. - Hariprasath Venkatram; Jon Guerber; Manideep Gande; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A Second-Order ΔΣ ADC Using Noise-Shaped Two-Step Integrating Quantizer. - Taehwan Oh; Nima Maghari; Un-Ku Moon (IEEE J. Solid State Circuits, 2013)

Inherently linear time symmetric pulse width modulation. - Yue Hu; Yang Xu 005; Un-Ku Moon (CICC, 2014)

Emerging analog-to-digital converters. - Nima Maghari; Un-Ku Moon (ESSCIRC, 2014)

Resistive correction of low output impedance high-speed current-steering DACs. - Spencer Leuenberger; Allen Waters; Un-Ku Moon (ICECS, 2014)

Analysis and performance trade-offs of linearity calibration for stochastic ADCs. - Allen Waters; Spencer Leuenberger; Farshad Farahbakhshian; Un-Ku Moon (ICECS, 2014)

LSB-first SAR ADC with bit-repeating for reduced energy consumption. - Allen Waters; Jerry Leung; Un-Ku Moon (ICECS, 2014)

Time amplifiers based on phase accumulation. - Yue Hu; Farshad Farahbakhshian; Un-Ku Moon (ISCAS, 2014)

Stochastic approximation register ADC. - Farshad Farahbakhshian; Allen Waters; Jason Muhlestein; Un-Ku Moon (NEWCAS, 2014)

A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier. - Hariprasath Venkatram; Taehwan Oh; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (VLSIC, 2014)

Blind Calibration Algorithm for Nonlinearity Correction Based on Selective Sampling. - Manideep Gande; Hariprasath Venkatram; Ho-Young Lee; Jon Guerber; Un-Ku Moon (IEEE J. Solid State Circuits, 2014)

A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information. - Taehwan Oh; Hariprasath Venkatram; Un-Ku Moon (IEEE J. Solid State Circuits, 2014)

Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells. - Skyler Weaver; Benjamin P. Hershberg; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW. - Allen Waters; Un-Ku Moon (A-SSCC, 2015)

Bit-error-rate analysis and mixed signal triple modular redundancy methods for data converters. - Jason Muhlestein; Hariprasath Venkatram; Jon Guerber; Allen Waters; Un-Ku Moon (ICECS, 2015)

A VCO-based spatial averaging stochastic ADC. - Hyuk Sun; Jason Muhlestein; Un-Ku Moon (ICECS, 2015)

Analysis of metastability errors in asynchronous SAR ADCs. - Allen Waters; Jason Muhlestein; Un-Ku Moon (ICECS, 2015)

Time-interleaved integrating quantizer incorporating channel coupling for speed and linearity enhancement. - Yue Hu; Spencer Leuenberger; Yang Xu 005; Un-Ku Moon (ISCAS, 2015)

A single OpAmp 2nd-Order ΔΣ ADC with a double integrating quantizer. - Spencer Leuenberger; Un-Ku Moon (ISCAS, 2015)

Selectable starting bit SAR ADC. - Jerry Leung; Allen Waters; Un-Ku Moon (ISCAS, 2015)

A ΔΣ ADC using an LSB-first SAR quantizer. - Allen Waters; Jerry Leung; Manideep Gande; Un-Ku Moon (ISCAS, 2015)

Highly linear continuous-time MASH ΔΣ ADC with dual VCO-based quantizers. - Yang Xu 005; Spencer Leuenberger; Un-Ku Moon (ISCAS, 2015)

MDLL/PLL dual-path clock generator. - Hyuk Sun; Un-Ku Moon (MWSCAS, 2015)

Practical modeling of comparator metastability for conventional and LSB-first SAR ADCs. - Allen Waters; Un-Ku Moon (MWSCAS, 2015)

Analysis of discrete-time charge-domain complex bandpass filter with accurately tunable center frequency. - Yang Xu 005; Hyuk Sun; Un-Ku Moon (MWSCAS, 2015)

A Continuous-Time ΔΣ ADC Utilizing Time Information for Two Cycles of Excess Loop Delay Compensation. - Yue Hu; Hariprasath Venkatram; Nima Maghari; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers. - Hyuk Sun; Jason Muhlestein; Spencer Leuenberger; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (A-SSCC, 2016)

Data converter reflections: 19 papers from the last ten years that deserve a second look. - David Robertson 002; Aaron Buchwald; Michael Flynn; Hae-Seung Lee; Un-Ku Moon; Boris Murmann (ESSCIRC, 2016)

A power efficient PLL with in-loop-bandwidth spread-spectrum modulation scheme using a charge-based discrete-time loop filter. - Hyuk Sun; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (ISCAS, 2016)

A 0.6mW 31MHz 4th-order low-pass filter with +29dBm IIP3 using self-coupled source follower based biquads in 0.18µm CMOS. - Yang Xu 005; Spencer Leuenberger; Praveen Kumar Venkatachala; Un-Ku Moon (VLSI Circuits, 2016)

Analysis of Metastability Errors in Conventional, LSB-First, and Asynchronous SAR ADCs. - Allen Waters; Jason Muhlestein; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone ring amplifier. - Spencer Leuenberger; Jason Muhlestein; Hyuk Sun; Praveen Kumar Venkatachala; Un-Ku Moon (CICC, 2017)

A 73dB SNDR 20MS/s 1.28mW SAR-TDC using hybrid two-step quantization. - Jason Muhlestein; Spencer Leuenberger; Hyuk Sun; Yang Xu 005; Un-Ku Moon (CICC, 2017)

A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLL. - Hyuk Sun; Kazuki Sobue; Koichi Hamashita; Tejasvi Anand; Un-Ku Moon (CICC, 2017)

A 0.65mW 20MHz 5th-order low-pass filter with +28.8dBm IIP3 using source follower coupling. - Yang Xu 005; Jason Muhlestein; Un-Ku Moon (CICC, 2017)

A multi-path ring amplifier with dynamic biasing. - Jason Muhlestein; Farshad Farahbakhshian; Praveen Kumar Venkatachala; Un-Ku Moon (ISCAS, 2017)

Voltage domain correction technique for timing skew errors in time interleaved ADCs. - Praveen Kumar Venkatachala; Ahmed ElShater; Yang Xu 005; Manar El-Chammas; Un-Ku Moon (ISCAS, 2017)

A highly compact wideband continuous-time transimpedance low-pass filter. - Yang Xu 005; Praveen Kumar Venkatachala; Un-Ku Moon (ISCAS, 2017)

Session 28 overview: Hybrid ADCs. - Tai-Cheng Lee; Bob Verbruggen; Un-Ku Moon (ISSCC, 2017)

Session 16 overview: Gigahertz data converters. - Jan Mulder; Paul Ferguson; Un-Ku Moon (ISSCC, 2017)

Pseudo-pseudo-differential circuits. - Tao He 001; Manjunath Kareppagoudr; Un-Ku Moon; Gabor C. Temes; Yi Zhang 023 (MWSCAS, 2017)

A Power Efficient SAR Algorithm for High Resolution ADCs. - Calvin Lee 001; Spencer Leuenberger; Praveen Kumar Venkatachala; Ahmed ElShater; Michael Oatman; Bohui Xiao; Un-Ku Moon (ISCAS, 2018)

An Empirical Study of the Settling Performance of Ring Amplifiers for Pipelined ADCs. - Spencer Leuenberger; Praveen Kumar Venkatachala; Ahmed ElShater; Michael Oatman; Calvin Lee 001; Bohui Xiao; Un-Ku Moon (ISCAS, 2018)

Process Invariant Biasing of Ring Amplifiers Using Deadzone Regulation Circuit. - Praveen Kumar Venkatachala; Spencer Leuenberger; Ahmed ElShater; Calvin Lee 001; Yang Xu 005; Bohui Xiao; Michael Oatman; Un-Ku Moon (ISCAS, 2018)

Passive Compensation for Improved Settling and Large Signal Stabilization of Ring Amplifiers. - Praveen Kumar Venkatachala; Spencer Leuenberger; Ahmed ElShater; Calvin Lee 001; Jason Muhlestein; Bohui Xiao; Michael Oatman; Un-Ku Moon (ISCAS, 2018)

Power Optimized Comparator Selecting Method For Stochastic ADC. - Bohui Xiao; Spencer Leuenberger; Praveen Kumar Venkatachala; Ahmed ElShater; Calvin Lee 001; Michael Oatman; Un-Ku Moon (ISCAS, 2018)

Session 22 overview: Gigahertz data converters: Data converter subcommittee. - Kostas Doris; Jan Westra; Un-Ku Moon (ISSCC, 2018)

Session 14 overview: High-resolution ADCs: Data converter subcommittee. - Matt Straayer; Seung-Tak Ryu; Un-Ku Moon (ISSCC, 2018)

An Oversampling Stochastic ADC Using VCO-Based Quantizers. - Hyuk Sun; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

An 80mA Capacitor-Less LDO with 6.5µA Quiescent Current and No Frequency Compensation Using Adaptive-Deadzone Ring Amplifier. - Bohui Xiao; Praveen Kumar Venkatachala; Yang Xu 005; Ahmed ElShater; Calvin Yoji Lee; Spencer Leuenberger; Qadeer Ahmad Khan; Un-Ku Moon (A-SSCC, 2019)

Simultaneous STF and NTF Estimation in CTΔΣ Modulators with ARMA-Model. - Hang Hu 009; Calvin Y. Lee; Ahmed ElShater; Zhiyuan Dai; Fan Ye 001; Un-Ku Moon (ISCAS, 2019)

Gm-Free Assisted Opamp Technique for Continuous Time Delta-Sigma Modulators. - Ahmed ElShater; Calvin Y. Lee; Praveen Kumar Venkatachala; Mohamed Dessouky; Un-Ku Moon (ISCAS, 2019)

Application of Ring-Amplifiers for Low-Power Wide-Bandwidth Digital Subsampling ADC-PLL. - Calvin Yoji Lee; Ahmed ElShater; Praveen Kumar Venkatachala; Hang Hu 009; Bohui Xiao; Un-Ku Moon (ISCAS, 2019)

Cascoded Ring Amplifiers for High Speed and High Accuracy Settling. - Calvin Yoji Lee; Praveen Kumar Venkatachala; Ahmed ElShater; Bohui Xiao; Hang Hu 009; Un-Ku Moon (ISCAS, 2019)

A 10mW 16b 15MS/s Two-Step SAR ADC with 95dB DR Using Dual-Deadzone Ring-Amplifier. - Ahmed ElShater; Calvin Yoji Lee; Praveen Kumar Venkatachala; Jason Muhlestein; Spencer Leuenberger; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (ISSCC, 2019)

A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier. - Ahmed ElShater; Praveen Kumar Venkatachala; Calvin Yoji Lee; Jason Muhlestein; Spencer Leuenberger; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (IEEE J. Solid State Circuits, 2019)

Noise Filtering and Linearization of Single-Ended Sampled-Data Circuits. - Tao He 001; Manjunath Kareppagoudr; Yi Zhang 023; Emanuel Caceres; Un-Ku Moon; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC with 85.1 dB DR and 91 dB SFDR. - Lukang Shi; Eashwar Thaigarajan; Rajiv Singh; Erhan Hancioglu; Un-Ku Moon; Gabor C. Temes (MWSCAS, 2020)

A 951-fsrms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator. - Hyuk Sun; Kazuki Sobue; Koichi Hamashita; Tejasvi Anand; Un-Ku Moon (IEEE J. Solid State Circuits, 2020)

A 77-dB-DR 0.65-mW 20-MHz 5th-Order Coupled Source Followers Based Low-Pass Filter. - Yang Xu 005; Hang Hu 009; Jason Muhlestein; Un-Ku Moon (IEEE J. Solid State Circuits, 2020)

A Charge-Domain Switched-Gm-C Band-Pass Filter Using Interleaved Semi-Passive Charge-Sharing Technique. - Yang Xu 005; Praveen Kumar Venkatachala; Yue Hu; Spencer Leuenberger; Gabor C. Temes; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Low-Distortion Correlated Level Shifting Sample-and-Hold Stage. - Alexander Pierce; Eashwar Thaigarajan; Rajiv Singh; Erhan Hancioglu; Un-Ku Moon; Gabor C. Temes (NEWCAS, 2021)

Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC With 82.6-dB SNDR and 90.9-dB SFDR. - Lukang Shi; Eashwar Thiagarajan; Rajiv Singh; Erhan Hancioglu; Un-Ku Moon; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A Pseudo-Pseudo-Differential ADC Achieving 105dB SNDR in 10kHz Bandwidth Using Ring Amplifier Based Integrators. - Calvin Yoji Lee; Praveen Kumar Venkatachala; Ahmed ElShater; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Switched-Capacitor Circuits. - David J. Allstot; Un-Ku Moon; Gabor C. Temes (CICC, 2022)

Passive Third Order Continuous-Time ΔΣ Modulator with Q Enhancement Technique. - Hang Hu 009; Vladimir Veselý; Un-Ku Moon (ISCAS, 2022)

Ultra-Low OSR Calibration Free MASH Noise Shaping SAR ADC. - Hang Hu 009; Vladimir Veselý; Un-Ku Moon (ISCAS, 2022)

A 0.0375mm2 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring-Amplifier-Based Integrator in 180nm CMOS. - Calvin Yoji Lee; Un-Ku Moon (ISSCC, 2022)

A 16- Bit 100kHz Bandwidth Pseudo-Pseudo-Differential Delta-Sigma ADC. - Manxin Li; Calvin Yoji Lee; Hanyu Wang; Gabor C. Temes; Un-Ku Moon (ISCAS, 2023)

A Rail-to-Rail 12MS 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting. - Manxin Li; Calvin Yoji Lee; Ahmed ElShater; Yuichi Miyahara; Kazuki Sobue; Koji Tomioka; Un-Ku Moon (ISSCC, 2023)

PLL-SAR: A New High-Speed Analog to Digital Converter Architecture. - Vladimir Veselý; Calvin Yoji Lee; Tejasvi Anand; Un-Ku Moon (MWSCAS, 2023)

A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting. - Manxin Li; Calvin Yoji Lee; Praveen Kumar Venkatachala; Ahmed ElShater; Yuichi Miyahara; Kazuki Sobue; Koji Tomioka; Un-Ku Moon (IEEE J. Solid State Circuits, 2023)

An Easy-to-Drive Discrete-Time ADC Topology Using Digital Predictive Level-Shifting. - Manxin Li; Runpeng Gao; Calder Wilson; Amartya Basak; Evan C. Markwell; Matthew L. Johnston; Un-Ku Moon (ISCAS, 2024)

Wideband Low-Distortion Noise-Coupled Delta-Sigma ADC. - Hanyu Wang; Faraz Adin; Un-Ku Moon; Gabor C. Temes (MWSCAS, 2024)

An 89.5 dB SNDR 500 kHz BW Largely Passive Fourth-Order Noise-Coupled Delta-Sigma Modulator. - Hanyu Wang; Faraz Adin; Un-Ku Moon; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)