Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements. - Unai Bidarte; Armando Astarloa; Aitzol Zuloaga; Jaime Jimenez; Iñigo Martínez de Alegría (FPL, 2003)

A Self-Reconfiguration Framework for Multiprocessor CSoPCs. - Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; José Luis Martín 001; Aitzol Zuloaga (FPL, 2004)

Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design. - Unai Bidarte; Armando Astarloa; José Luis Martín 001; Jon Andreu (FPL, 2004)

High Throughput Serpent Encryption Implementation. - Jesús Lázaro 001; Armando Astarloa; Jagoba Arias; Unai Bidarte; Carlos Cuadrado (FPL, 2004)

Co-simulation Virtual Platform for Reconfigurable Multiprocessor Hybrid Cores Development. - Armando Astarloa; Jesús Lázaro 001; Jagoba Arias; Unai Bidarte; Aitzol Zuloaga (MSV/AMCS, 2004)

Hardware implementation of optical flow constraint equation using FPGAs. - José L. Martín-Sánchez; Aitzol Zuloaga; Carlos Cuadrado; Jesús Lázaro 001; Unai Bidarte (Comput. Vis. Image Underst., 2005)

Multiprocessor SoPC-Core for FAT volume computation. - Armando Astarloa; Unai Bidarte; Jesús Lázaro 001; Aitzol Zuloaga; Jagoba Arias (Microprocess. Microsystems, 2005)

Comparison of two designs for the multifunction vehicle bus. - Jaime Jimenez; José Luis Martín 001; Aitzol Zuloaga; Unai Bidarte; Jagoba Arias (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Hardware architecture for a general regression neural network coprocessor. - Jesús Lázaro 001; Jagoba Arias; Armando Astarloa; Unai Bidarte; Aitzol Zuloaga (Neurocomputing, 2007)

Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs. - Armando Astarloa; Aitzol Zuloaga; Unai Bidarte; José Luis Martín 001; Jesús Lázaro 001; Jaime Jimenez (J. Syst. Archit., 2007)

Design of a Master Device for the Multifunction Vehicle Bus. - Jaime Jimenez; José Luis Martín 001; Unai Bidarte; Armando Astarloa; Aitzol Zuloaga (IEEE Trans. Veh. Technol., 2007)

Secure Ethernet Point-to-Point Links for Autonomous Electronic Ballot Boxes. - Armando Astarloa; Unai Bidarte; Jaime Jimenez; Jesús Lázaro 001; Iñigo Martínez de Alegría (ATC, 2008)

Configurable-System-on-Programmable-Chip for Power Electronics Control Applications. - Armando Astarloa; Unai Bidarte; Jesús Lázaro 001; Jon Andreu; José Luis Martín 001 (ReConFig, 2008)

AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications. - Jesús Lázaro 001; Armando Astarloa; Unai Bidarte; Jaime Jimenez; Aitzol Zuloaga (ARC, 2009)

DNAX-BCU: An Un-clonable Cost-conscious SoPC Implementation for Bus Coupling Units of the European Installation Bus. - Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; Aitzol Zuloaga; Jaime Jimenez (ICDCS Workshops, 2009)

PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems. - Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; Aitzol Zuloaga; Jaime Jimenez (ReConFig, 2009)

Overview of FPGA-Based Multiprocessor Systems. - Taho Dorta; Jaime Jimenez; José Luis Martín 001; Unai Bidarte; Armando Astarloa (ReConFig, 2009)

An Autonomous Fault Tolerant System for CAN Communications. - Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; Aitzol Zuloaga; José Luis Martín 001 (IEA/AIE (3), 2010)

Reconfigurable Multiprocessor Systems: A Review. - Taho Dorta; Jaime Jimenez; José Luis Martín 001; Unai Bidarte; Armando Astarloa (Int. J. Reconfigurable Comput., 2010)

Robustness Analysis of Different AES Implementations on SRAM Based FPGAs. - Uli Kretzschmar; Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; Jaime Jimenez (ReConFig, 2011)

I2CSec: A secure serial Chip-to-Chip communication protocol. - Jesús Lázaro 001; Armando Astarloa; Aitzol Zuloaga; Unai Bidarte; Jaime Jimenez (J. Syst. Archit., 2011)

System-on-Chip implementation of Reliable Ethernet Networks nodes. - Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; Aitzol Zuloaga; Mikel Idirin (IECON, 2013)

Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor. - Julen Gomez-Cornejo; Aitzol Zuloaga; Uli Kretzschmar; Unai Bidarte; Jaime Jimenez (IECON, 2013)

Fast and accurate SEU-tolerance characterization method for Zynq SoCs. - Igor Villata; Unai Bidarte; Uli Kretzschmar; Armando Astarloa; Jesús Lázaro 001 (FPL, 2014)

FPGA based nodes for sub-microsecond synchronization of cyber-physical production systems on high availability ring networks. - Armando Astarloa; Naiara Moreira; Unai Bidarte; Marcelo Urbina; David Modrono (ReConFig, 2015)

Intelligent gateway for Industry 4.0-compliant production. - Armando Astarloa; Unai Bidarte; Jaime Jimenez; Aitzol Zuloaga; Jesús Lázaro 001 (IECON, 2016)

Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs. - Uli Kretzschmar; Julen Gomez-Cornejo; Armando Astarloa; Unai Bidarte; Javier Del Ser (Reliab. Eng. Syst. Saf., 2016)

Cyber-Physical Production System Gateway Based on a Programmable SoC Platform. - Marcelo Urbina; Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; Igor Villalta; Mikel Rodriguez (IEEE Access, 2017)

Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs. - Igor Villalta; Unai Bidarte; Julen Gomez-Cornejo; Jesús Lázaro 001; Armando Astarloa (Microelectron. Reliab., 2017)

On the Utilization of System-on-Chip Platforms to Achieve Nanosecond Synchronization Accuracies in Substation Automation Systems. - Naiara Moreira; Jesús Lázaro 001; Unai Bidarte; Jaime Jimenez; Armando Astarloa (IEEE Trans. Smart Grid, 2017)

System-on-Programmable-Chip AES-GCM implementation for wire-speed cryptography for SAS. - Mikel Rodriguez; Armando Astarloa; Jesús Lázaro 001; Unai Bidarte; Jaime Jimenez (DCIS, 2018)

SEU emulation in industrial SoCs combining microprocessor and FPGA. - Igor Villalta; Unai Bidarte; Julen Gomez-Cornejo; Jaime Jimenez; Jesús Lázaro 001 (Reliab. Eng. Syst. Saf., 2018)

Fast and efficient FPGA prototype system for embedded control algorithms in electric traction. - Carlos Cuadrado; Iñigo Kortabarria; Jesús Lázaro 001; Unai Bidarte; Jaime Jiménez (DCIS, 2019)

Smart Sensor: SoC Architecture for the Industrial Internet of Things. - Marcelo Urbina; Tatiana Acosta; Jesús Lázaro 001; Armando Astarloa; Unai Bidarte (IEEE Internet Things J., 2019)

Evaluating the OpenAMP framework in real-time embedded SoC platforms. - Sara Alonso; Jesús Lázaro 001; Jaime Jimenez; Leire Muguira; Unai Bidarte (DCIS, 2021)

A Fixed-Latency Architecture to Secure GOOSE and Sampled Value Messages in Substation Systems. - Mikel Rodriguez; Jesús Lázaro 001; Unai Bidarte; Jaime Jiménez; Armando Astarloa (IEEE Access, 2021)

Fast and efficient address search in System-on-a-Programmable-Chip using binary trees. - Jesús Lázaro 001; Unai Bidarte; Leire Muguira; Carlos Cuadrado; Jaime Jiménez (Comput. Electr. Eng., 2021)

The influence of virtualization on real-time systems' interrupts in embedded SoC platforms. - Sara Alonso; Jesús Lázaro 001; Jaime Jiménez; Leire Muguira; Unai Bidarte (DCIS, 2022)

Embedded firewall for on-chip bus transactions. - Jesús Lázaro 001; Unai Bidarte; Leire Muguira; Armando Astarloa; Jaime Jiménez (Comput. Electr. Eng., 2022)

Timing requirements on multi-processing and reconfigurable embedded systems with multiple environments. - Sara Alonso; Jesús Lázaro 001; Jaime Jiménez; Leire Muguira; Unai Bidarte (DCIS, 2023)