Low power logic synthesis for XOR based circuits. - Unni Narayanan; C. L. Liu 001 (ICCAD, 1997)

Low power multiplexer decomposition. - Unni Narayanan; Hon Wai Leong; Ki-Seok Chung; Chien-Liang Liu (ISLPED, 1997)

Low power logic synthesis under a general delay model. - Unni Narayanan; Peichen Pan; C. L. Liu 001 (ISLPED, 1998)

Algorithmic Techniques for Logic Synthesis of Low Power VLSI Circuits - Unni Narayanan (1998)

Automated Phase Assignment for the Synthesis of Low Power Domino Circuits. - Priyadarshan Patra; Unni Narayanan (DAC, 1999)

Characterizing Individual Gate Power Sensitivity in Low Power Design. - Unni Narayanan; Georgios I. Stamoulis; Rabindra K. Roy (VLSI Design, 1999)

Domino logic synthesis minimizing crosstalk. - Ki-Wook Kim; Unni Narayanan; Sung-Mo Kang (DAC, 2000)

Noise-aware power optimization for on-chip interconnect. - Ki-Wook Kim; Seong-Ook Jung; Unni Narayanan; C. L. Liu 001; Sung-Mo Kang (ISLPED, 2000)

Decomposition of Bus-Invert Coding for Low-Power I/O. - Sungpack Hong; Taewhan Kim 001; Unni Narayanan; Ki-Seok Chung (J. Circuits Syst. Comput., 2000)

Enhanced bus invert encodings for low-power. - Unni Narayanan; Ki-Seok Chung; Taewhan Kim 001 (ISCAS (5), 2002)

Noise-aware interconnect power optimization in domino logic synthesis. - Ki-Wook Kim; Seong-Ook Jung; Unni Narayanan; C. L. Liu 001; Sung-Mo Kang (IEEE Trans. Very Large Scale Integr. Syst., 2003)