Efficient Systolic Array for Matrix Multiplication. - Fabian Klass; Uri C. Weiser (ICPP (3), 1991)

MMX technology extension to the Intel architecture. - Alex Peleg; Uri C. Weiser (IEEE Micro, 1996)

Intel's MMX™ technology-a new instruction set extension. - Oded Lempel; Alex Peleg; Uri C. Weiser (COMPCON, 1997)

Intel MMX for Multimedia PCs. - Alex Peleg; Sam Wilkie; Uri C. Weiser (Commun. ACM, 1997)

Correlated Load-Address Predictors. - Michael Bekerman; Stéphan Jourdan; Ronny Ronen; Gilad Kirshenboim; Lihu Rappoport; Adi Yoaz; Uri C. Weiser (ISCA, 1999)

Interconnect-power dissipation in a microprocessor. - Nir Magen; Avinoam Kolodny; Uri C. Weiser; Nachum Shamir (SLIP, 2004)

Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors. - Tomer Y. Morad; Uri C. Weiser; A. Kolodnyt; Mateo Valero; Eduard Ayguadé (IEEE Comput. Archit. Lett., 2006)

Nahalal: Cache Organization for Chip Multiprocessors. - Zvika Guz; Idit Keidar; Avinoam Kolodny; Uri C. Weiser (IEEE Comput. Archit. Lett., 2007)

Utilizing shared data in chip multiprocessors with the nahalal architecture. - Zvika Guz; Idit Keidar; Avinoam Kolodny; Uri C. Weiser (SPAA, 2008)

Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors. - A. Elyada; Ran Ginosar; Uri C. Weiser (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Multiple clock and voltage domains for chip multi processors. - Efraim Rotem; Avi Mendelson; Ran Ginosar; Uri C. Weiser (MICRO, 2009)

Many-Core vs. Many-Thread Machines: Stay Away From the Valley. - Zvika Guz; Evgeny Bolotin; Idit Keidar; Avinoam Kolodny; Avi Mendelson; Uri C. Weiser (IEEE Comput. Archit. Lett., 2009)

Threads vs. caches: Modeling the behavior of parallel workloads. - Zvika Guz; Oved Itzhak; Idit Keidar; Avinoam Kolodny; Avi Mendelson; Uri C. Weiser (ICCD, 2010)

Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors. - Tomer Y. Morad; Avinoam Kolodny; Uri C. Weiser (PAAP, 2010)

Memristor-based IMPLY logic design procedure. - Shahar Kvatinsky; Avinoam Kolodny; Uri C. Weiser; Eby G. Friedman (ICCD, 2011)

Multi-Amdahl: Optimal Resource Sharing with Multiple Program Execution Segments - Tsahee Zidenberg; Isaac Keslassy; Uri C. Weiser (CoRR, 2011)

MultiAmdahl: How Should I Divide My Heterogenous Chip? - Tsahee Zidenberg; Isaac Keslassy; Uri C. Weiser (IEEE Comput. Archit. Lett., 2012)

Task Scheduling Based On Thread Essence and Resource Limitations. - Tomer Y. Morad; Avinoam Kolodny; Uri C. Weiser (J. Comput., 2012)

Optimal Resource Allocation with MultiAmdahl. - Tsahee Zidenberg; Isaac Keslassy; Uri C. Weiser (Computer, 2013)

TEAM: ThrEshold Adaptive Memristor Model. - Shahar Kvatinsky; Eby G. Friedman; Avinoam Kolodny; Uri C. Weiser (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Loop-Aware Memory Prefetching Using Code Block Working Sets. - Adi Fuchs; Shie Mannor; Uri C. Weiser; Yoav Etsion (MICRO, 2014)

Energy management of highly dynamic server workloads in an heterogeneous data center. - Efraim Rotem; Uri C. Weiser; Avi Mendelson; Ahmad Yasin; Ran Ginosar (PATMOS, 2014)

Memristor-Based Multithreading. - Shahar Kvatinsky; Yuval H. Nacson; Yoav Etsion; Eby G. Friedman; Avinoam Kolodny; Uri C. Weiser (IEEE Comput. Archit. Lett., 2014)

Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator SoC. - Amir Morad; Tomer Y. Morad; Leonid Yavits; Ran Ginosar; Uri C. Weiser (IEEE Comput. Archit. Lett., 2014)

Energy Aware Race to Halt: A Down to EARtH Approach for Platform Energy Management. - Efraim Rotem; Ran Ginosar; Uri C. Weiser; Avi Mendelson (IEEE Comput. Archit. Lett., 2014)

MAGIC - Memristor-Aided Logic. - Shahar Kvatinsky; Dmitry Belousov; Slavik Liman; Guy Satat; Nimrod Wald; Eby G. Friedman; Avinoam Kolodny; Uri C. Weiser (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies. - Shahar Kvatinsky; Guy Satat; Nimrod Wald; Eby G. Friedman; Avinoam Kolodny; Uri C. Weiser (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Semantic locality and context-based prefetching using reinforcement learning. - Leeor Peled; Shie Mannor; Uri C. Weiser; Yoav Etsion (ISCA, 2015)

Peripheral Memory: A Technique for Fighting Memory Bandwidth Bottleneck. - Leonid Azriel; Avi Mendelson; Uri C. Weiser (IEEE Comput. Archit. Lett., 2015)

Power and thermal constraints of modern system-on-a-chip computer. - Efraim Rotem; Ran Ginosar; Avi Mendelson; Uri C. Weiser (Microelectron. J., 2015)

Potential future research in computing: Heterogeneous systems, memory subsystems - Process-in-storage, or not to process-in-storage? That is the question. - Uri C. Weiser (SAMOS, 2016)

H-EARtH: Heterogeneous Multicore Platform Energy Management. - Efraim Rotem; Uri C. Weiser; Avi Mendelson; Ran Ginosar; Eliezer Weissmann; Yoni Aizik (Computer, 2016)

Convex Optimization of Real Time SoC. - Leonid Yavits; Amir Morad; Ran Ginosar; Uri C. Weiser (CoRR, 2016)

EFS: Energy-Friendly Scheduler for memory bandwidth constrained systems. - Tomer Y. Morad; Noam Shalev; Idit Keidar; Avinoam Kolodny; Uri C. Weiser (J. Parallel Distributed Comput., 2016)

Optimizing Read-Once Data Flow in Big-Data Applications. - Tomer Y. Morad; Gil Shomron; Mattan Erez; Avinoam Kolodny; Uri C. Weiser (IEEE Comput. Archit. Lett., 2017)

Resistive Address Decoder. - Leonid Yavits; Uri C. Weiser; Ran Ginosar (IEEE Comput. Archit. Lett., 2017)

MultiAmdahl: Optimal Resource Allocation in Heterogeneous Architectures. - Leonid Yavits; Amir Morad; Uri C. Weiser; Ran Ginosar (CoRR, 2017)

A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. - Roman Kaplan; Leonid Yavits; Ran Ginosar; Uri C. Weiser (IEEE Micro, 2017)

Insights from the 2016 Eckert-Mauchly Award Recipient. - Uri C. Weiser (IEEE Micro, 2017)

Towards Memory Prefetching with Neural Networks: Challenges and Insights. - Leeor Peled; Uri C. Weiser; Yoav Etsion (CoRR, 2018)

Exploiting Spatial Correlation in Convolutional Neural Networks for Activation Value Prediction. - Gil Shomron; Uri C. Weiser (CoRR, 2018)

SMT-SA: Simultaneous Multithreading in Systolic Arrays. - Gil Shomron; Tal Horowitz; Uri C. Weiser (IEEE Comput. Archit. Lett., 2019)

Spatial Correlation and Value Prediction in Convolutional Neural Networks. - Gil Shomron; Uri C. Weiser (IEEE Comput. Archit. Lett., 2019)

Thanks for Nothing: Predicting Zero-Valued Activations with Lightweight Convolutional Neural Networks. - Gil Shomron; Ron Banner; Moran Shkolnik; Uri C. Weiser (ECCV (10), 2020)

Non-Blocking Simultaneous Multithreading: Embracing the Resiliency of Deep Neural Networks. - Gil Shomron; Uri C. Weiser (MICRO, 2020)

Robust Quantization: One Model to Rule Them All. - Moran Shkolnik; Brian Chmiel; Ron Banner; Gil Shomron; Yury Nahshan; Alex M. Bronstein; Uri C. Weiser (NeurIPS, 2020)

Semantic prefetching using forecast slices. - Leeor Peled; Uri C. Weiser; Yoav Etsion (CoRR, 2020)

Post-Training BatchNorm Recalibration. - Gil Shomron; Uri C. Weiser (CoRR, 2020)

A Neural Network Prefetcher for Arbitrary Memory Access Patterns. - Leeor Peled; Uri C. Weiser; Yoav Etsion (ACM Trans. Archit. Code Optim., 2020)

Post-Training Sparsity-Aware Quantization. - Gil Shomron; Freddy Gabbay; Samer Kurzum; Uri C. Weiser (NeurIPS, 2021)

Enhancing DNN Training Efficiency Via Dynamic Asymmetric Architecture. - Samer Kurzum; Gil Shomron; Freddy Gabbay; Uri C. Weiser (IEEE Comput. Archit. Lett., 2023)

Enhancing DNN Computational Efficiency via Decomposition and Approximation. - Ori Schweitzer; Uri C. Weiser; Freddy Gabbay (IEEE Access, 2024)