A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM. - Seunghwan Hong; Chang-Hyun Bae; Yoo-Chang Sung; Jaewoong Kim; Junsub Yoon; Sangwoo Kim; Jin-Hyeok Baek; Cheongryong Cho; Useung Shin; Sang-Kyeom Kim; Hwan-Chul Jung; Ho-Jun Chang; et al. (VLSI Circuits, 2021)

A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features. - Yesin Ryu; Young-Cheon Kwon; Jaehoon Lee 005; Sung-Gi Ahn; Jaewon Park; Kijun Lee; Yu Ho Choi; Han-Won Cho; Jae San Kim; Jungyu Lee 002; Haesuk Lee; Seung Ho Song; et al. (VLSI Technology and Circuits, 2022)

A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features. - Yesin Ryu; Sung-Gi Ahn; Jaehoon Lee 005; Jaewon Park; Yong-Ki Kim; Hyochang Kim; Yeong Geol Song; Han-Won Cho; Sunghye Cho; Seung Ho Song; Haesuk Lee; Useung Shin; et al. (IEEE J. Solid State Circuits, 2023)