Applying Razor Flip-Flops to SRAM Read Circuits. - Ushio Jimbo; Junji Yamada; Ryota Shioya; Masahiro Goshima (IEICE Trans. Electron., 2017)

Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology. - Junji Yamada; Ushio Jimbo; Ryota Shioya; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Electron., 2017)

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency. - Junji Yamada; Ushio Jimbo; Ryota Shioya; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Inf. Syst., 2017)

Application of Timing Fault Detection to Rocket Core on FPGA. - Ushio Jimbo; Ryota Shioya; Masahiro Goshima (CANDAR Workshops, 2018)

Bank-Aware Instruction Scheduler for a Multibanked Register File. - Junji Yamada; Ushio Jimbo; Ryota Shioya; Masahiro Goshima; Shuichi Sakai (J. Inf. Process., 2018)