Design and Implementation of Low Power and Area Efficient Architecture for High Performance ALU. - Usthulamuri Penchalaiah; V. G. Siva Kumar (Parallel Process. Lett., 2022)

A deep learning based latency aware predictive routing model for network-on-chip architectures. - M. Venkata Sudhakar; P. Rahul Reddy; Usthulamuri Penchalaiah; P. Raghava Reddy (Int. J. Commun. Syst., 2023)