A Multilevel Computing Architecture for Embedded Multimedia Applications. - Faraydon Karim; Alain Mellan; Anh Nguyen; Utku Aydonat; Tarek S. Abdelrahman (IEEE Micro, 2004)

Hardware Support for Relaxed Concurrency Control in Transactional Memory. - Utku Aydonat; Tarek S. Abdelrahman (MICRO, 2010)

Parallelization of multimedia applications on the multi-level computing architecture. - Utku Aydonat; Tarek S. Abdelrahman (J. Embed. Comput., 2011)

From opencl to high-performance hardware on FPGAS. - Tomasz S. Czajkowski; Utku Aydonat; Dmitry Denisenko; John Freeman; Michael Kinsner; David Neto; Jason Wong; Peter Yiannacouras; Deshanand P. Singh (FPL, 2012)

Relaxed Concurrency Control in Software Transactional Memory. - Utku Aydonat; Tarek S. Abdelrahman (IEEE Trans. Parallel Distributed Syst., 2012)

An OpenCL™ Deep Learning Accelerator on Arria 10. - Utku Aydonat; Shane O'Connell; Davor Capalija; Andrew C. Ling; Gordon R. Chiu (FPGA, 2017)

Creating High Performance Applications with Intel's FPGA OpenCL™ SDK. - Andrew C. Ling; Utku Aydonat; Shane O'Connell; Davor Capalija; Gordon R. Chiu (IWOCL, 2017)

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). - Eriko Nurvitadhi; Jeffrey J. Cook; Asit K. Mishra; Debbie Marr; Kevin Nealis; Philip Colangelo; Andrew C. Ling; Davor Capalija; Utku Aydonat; Sergey Y. Shumarayev; Aravind Dasu (FPGA, 2018)

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. - Eriko Nurvitadhi; Jeffrey J. Cook; Asit K. Mishra; Debbie Marr; Kevin Nealis; Philip Colangelo; Andrew C. Ling; Davor Capalija; Utku Aydonat; Aravind Dasu; Sergey Y. Shumarayev (FPL, 2018)

Compute Substrate for Software 2.0. - Jasmina Vasiljevic; Ljubisa Bajic; Davor Capalija; Stanislav Sokorac; Dragoljub Ignjatovic; Lejla Bajic; Milos Trajkovic; Ivan Hamer; Ivan Matosevic; Aleksandar Cejkov; Utku Aydonat; Tony Zhou; et al. (IEEE Micro, 2021)