eeDTLS: Energy-Efficient Datagram Transport Layer Security for the Internet of Things. - Utsav Banerjee; Chiraag Juvekar; Samuel H. Fuller; Anantha P. Chandrakasan (GLOBECOM, 2017)

An energy-efficient reconfigurable DTLS cryptographic engine for End-to-End security in iot applications. - Utsav Banerjee; Chiraag Juvekar; Andrew Wright; Arvind 001; Anantha P. Chandrakasan (ISSCC, 2018)

An Energy-Efficient Configurable Lattice Cryptography Processor for the Quantum-Secure Internet of Things. - Utsav Banerjee; Abhishek Pathak; Anantha P. Chandrakasan (ISSCC, 2019)

Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols (Extended Version). - Utsav Banerjee; Tenzin S. Ukyab; Anantha P. Chandrakasan (IACR Cryptol. ePrint Arch., 2019)

An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications. - Utsav Banerjee; Andrew Wright; Chiraag Juvekar; Madeleine Waller; Arvind 001; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2019)

Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols. - Utsav Banerjee; Tenzin S. Ukyab; Anantha P. Chandrakasan (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019)

A Low-Power Dual-Factor Authentication Unit for Secure Implantable Devices. - Saurav Maji; Utsav Banerjee; Samuel H. Fuller; Mohamed R. Abdelhamid; Phillip M. Nadeau; Rabia Tugce Yazicigil; Anantha P. Chandrakasan (CICC, 2020)

Efficient Post-Quantum TLS Handshakes using Identity-Based Key Exchange from Lattices. - Utsav Banerjee; Anantha P. Chandrakasan (ICC, 2020)

Accelerating Post-Quantum Cryptography using an Energy-Efficient TLS Crypto-Processor. - Utsav Banerjee; Siddharth Das; Anantha P. Chandrakasan (ISCAS, 2020)

Securing Embedded Medical Devices using Dual-Factor Authentication. - Saurav Maji; Utsav Banerjee; Samuel H. Fuller; Rabia Tugce Yazicigil; Anantha P. Chandrakasan (CBMS, 2021)

A Low-Power Elliptic Curve Pairing Crypto-Processor for Secure Embedded Blockchain and Functional Encryption. - Utsav Banerjee; Anantha P. Chandrakasan (CICC, 2021)

Leaky Nets: Recovering Embedded Neural Network Models and Inputs Through Simple Power and Timing Side-Channels - Attacks and Defenses. - Saurav Maji; Utsav Banerjee; Anantha P. Chandrakasan (IEEE Internet Things J., 2021)

Efficient Algorithms, Protocols and Hardware Architectures for Next-Generation Cryptography in Embedded Systems. - Utsav Banerjee (2021)

Embedded Software Implementation of Privacy Preserving Matrix Computation using Elliptic Curve Cryptography for IoT Applications. - Faiek Ahsan; Utsav Banerjee (ANTS, 2022)

Wireless, Batteryless, and Secure Implantable System-on-a-Chip for 1.37mmHg Strain Sensing with Bandwidth Reconfigurability for Cross-Tissue Adaptation. - Mohamed R. Abdelhamid; Unsoo Ha; Utsav Banerjee; Fadel Adib; Anantha P. Chandrakasan (CICC, 2022)

Design and Analysis of a Scalable and Efficient Quantum Circuit for LWE Matrix Arithmetic. - Chao Lu; Utsav Banerjee; Kanad Basu (ICCD, 2022)

A ThreshoId-ImpIementation-Based Neural-Network Accelerator Securing Model Parameters and Inputs Against Power Side-Channel Attacks. - Saurav Maji; Utsav Banerjee; Samuel H. Fuller; Anantha P. Chandrakasan (ISSCC, 2022)

A Low-Power BLS12-381 Pairing Crypto-Processor for Internet-of-Things Security Applications. - Utsav Banerjee; Anantha P. Chandrakasan (CoRR, 2022)

Power-Based Side-Channel Attack for AES Key Extraction on the ATMega328 Microcontroller. - Utsav Banerjee; Lisa Ho; Skanda Koppula (CoRR, 2022)

A 1.54mm2 Wake-Up Receiver Based on THz Carrier Wave and Integrated Cryptographic Authentication. - Eunseok Lee 002; Muhammad Ibrahim Wasiq Khan; Xibi Chen; Utsav Banerjee; Nathan M. Monroe; Rabia Tugce Yazicigil; Ruonan Han 001; Anantha P. Chandrakasan (CICC, 2023)

Privacy-Preserving Edge Computing from Pairing-Based Inner Product Functional Encryption. - Utsav Banerjee (GLOBECOM, 2023)

Tyche: A Compact and Configurable Accelerator for Scalable Probabilistic Computing on FPGA. - Yashash Jain; Utsav Banerjee (HPEC, 2023)

Energy-Efficient Cryptographic Acceleration using Hardware-Software Co-Design with RISC-V. - Utsav Banerjee (iSES, 2023)

A Threshold Implementation-Based Neural Network Accelerator With Power and Electromagnetic Side-Channel Countermeasures. - Saurav Maji; Utsav Banerjee; Samuel H. Fuller; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2023)

A High-Performance Curve25519 and Curve448 Unified Elliptic Curve Cryptography Accelerator. - Aniket Banerjee; Utsav Banerjee (HPEC, 2024)

pc-COP: An Efficient and Configurable 2048-p-Bit Fully-Connected Probabilistic Computing Accelerator for Combinatorial Optimization. - Kiran Magar; Shreya Bharathan; Utsav Banerjee (HPEC, 2024)

Energy-Efficient and Secure Clustering with Post-Quantum DTLS in Wireless Sensor Networks. - Utsav Banerjee (ISCC, 2024)

A 1.54-mm2, 264-GHz Wake-Up Receiver With Integrated Cryptographic Authentication for Ultra-Miniaturized Platforms. - Eunseok Lee 002; Muhammad Ibrahim Wasiq Khan; Xibi Chen; Utsav Banerjee; Nathan M. Monroe; Rabia Tugce Yazicigil; Ruonan Han 001; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2024)

QuBEC: Boosting Equivalence Checking for Quantum Circuits With QEC Embedding. - Chao Lu; Navnil Choudhury; Utsav Banerjee; Abdullah Ash-Saki; Kanad Basu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A Unified Hardware Accelerator for Fast Fourier Transform and Number Theoretic Transform. - Rishabh Shrivastava; Chaitanya Prasad Ratnala; Durga Manasa Puli; Utsav Banerjee (ICASSP, 2025)

Fast Plaintext-Ciphertext Matrix Multiplication from Additively Homomorphic Encryption. - Krishna Sai Tarun Ramapragada; Utsav Banerjee (IACR Commun. Cryptol., 2025)

Writing a Good Security Paper for ISSCC (2025). - Utsav Banerjee; Chiraag Juvekar; Yong Ki Lee; Leibo Liu; Sanu Mathew; Thomas Pöppelmann; Shreyas Sen; Takeshi Sugawara 001; Ingrid Verbauwhede; Rabia Tugce Yazicigil (CoRR, 2025)