Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count. - M. Saad Bin Arif; Uvais Mustafa; Shahrin Bin Md. Ayob; José Rodríguez 001; Abdul Nadeem; Mohamed Abdelrahem (IEEE Access, 2021)

Asymmetrical 21-level inverter topology with minimum variety of dc sources and reduced component counts. - M. Saad Bin Arif; Uvais Mustafa; Shahbaz Ahmad; Shahrin Bin Md. Ayob; Ratil Hasnat Ashique; Mohammad Tayyab (Int. J. Circuit Theory Appl., 2023)

On Accelerated Degradation of DC-Link Film Capacitors and Data-Based Lifetime Estimation. - Angel E. Peña-Quintal; Uvais Mustafa; Chris Gerada; Md Rishad Ahmed (IEEE Access, 2024)