Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes. - V. Bharath Sreenivasulu; Vadthiya Narendar (Microelectron. J., 2021)

Characterization for Sub-5nm Technology Nodes of Junctionless Gate-All-Around Nanowire FETs. - Aruru Sai Kumar; M. Deekshana; V. Bharath Sreenivasulu; Rajendra Prasad Somineni; D. Kanthi Sudha (ICCCNT, 2022)

Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison. - V. Bharath Sreenivasulu; Aruna Kumari Neelam; Sekhar Reddy Kola; Jawar Singh; Yiming Li 005 (IEEE Access, 2023)

Investigation on effect of AlN barrier thickness and lateral scalability of Fe-doped recessed T-gate AlN/GaN/SiC HEMT with polarization-graded back barrier for future RF electronic applications. - B. Mounika; J. Ajayan; Sandip Bhattacharya; D. Nirmal; V. Bharath Sreenivasulu; N. Aruna Kumari (Microelectron. J., 2023)

Performance Comparison of Nanosheet FET, CombFET, and TreeFET: Device and Circuit Perspective. - Aruna Kumari Neelam; V. Bharath Sreenivasulu; Vikas Vijayvargiya; Abhishek Kumar Upadhyay; J. Ajayan; M. Uma (IEEE Access, 2024)

Spacer Dielectric Analysis of Multi-Channel Nanosheet FET for Nanoscale Applications. - Asisa Kumar Panigrahy; Veera Venkata Sai Amudalapalli; Depuru Shobha Rani; Muralidhar Nayak Bhukya; Hima Bindu Valiveti; V. Bharath Sreenivasulu; Raghunandan Swain (IEEE Access, 2024)

Benchmarking of Multi-Bridge-Channel FETs Toward Analog and Mixed-Mode Circuit Applications. - V. Bharath Sreenivasulu; Aruna Kumari Neelam; Asisa Kumar Panigrahy; Lokesh Vakkalakula; Jawar Singh; Shiv Govind Singh (IEEE Access, 2024)