Analysis of Cache(SRAM) Memory for Core i™ 7 Processor. - Reeya Agrawal; V. K. Tomar (ICCCNT, 2018)

Performance Evaluation of 6T, 7T, 8T, and 9T SRAM cell Topologies at 90 nm Technology Node. - Deepak Mittal; V. K. Tomar (ICCCNT, 2020)

Design of a Stable Low Power 11-T Static Random Access Memory Cell. - Ashish Sachdeva; V. K. Tomar (J. Circuits Syst. Comput., 2020)

Design of 10T SRAM cell with improved read performance and expanded write margin. - Ashish Sachdeva; V. K. Tomar (IET Circuits Devices Syst., 2021)

Design of Low Power with Expanded Noise Margin Subthreshold 12T SRAM Cell for Ultra-Low Power Devices. - Harekrishna Kumar; V. K. Tomar (J. Circuits Syst. Comput., 2021)

Design of Low Power Half Select Free 10T Static Random-Access Memory Cell. - Ashish Sachdeva; V. K. Tomar (J. Circuits Syst. Comput., 2021)

A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era. - Harekrishna Kumar; V. K. Tomar (Wirel. Pers. Commun., 2021)

A Multi-bit Error Upset Immune 12T SRAM Cell for 5G Satellite Communications. - Ashish Sachdeva; V. K. Tomar (Wirel. Pers. Commun., 2021)

Design of Low Leakage 9T SRAM Cell with Improved Performance for Ultra-Low Power Devices. - Harekrishna Kumar; V. K. Tomar (J. Circuits Syst. Comput., 2022)

Characterization of Stable 12T SRAM with Improved Critical Charge. - Ashish Sachdeva; V. K. Tomar (J. Circuits Syst. Comput., 2022)

Design of a soft error hardened SRAM cell with improved access time for embedded systems. - V. K. Tomar; Ashish Sachdeva (Microprocess. Microsystems, 2022)

10T SRAM cell Analysis for improved Read and Write Noise Margin. - Saloni Bansal; V. K. Tomar (ICCCNT, 2023)