An Optimal Algorithm for Reconstructing a Binary Tree. - V. Kamakoti 001; C. Pandu Rangan (Inf. Process. Lett., 1992)

Efficient Randomized Parallel Algorithm for the Closest Pair Problem in D-dimension. - P. Jagan Mohan; V. Kamakoti 001; C. Pandu Rangan (IFIP Congress (1), 1994)

Efficient Randomized Incremental Algorithm For The Closest Pair Problem Using Leafary Trees. - V. Kamakoti 001; Kamala Krithivasan; C. Pandu Rangan (COCOON, 1995)

Efficient Parallel Algorithms for Permutation Graphs. - K. Arvind; V. Kamakoti 001; C. Pandu Rangan (J. Parallel Distributed Comput., 1995)

An Efficient Randomized Algorithm for the Closest Pair Problem on Colored Point Sets. - V. Kamakoti 001; Kamala Krithivasan; C. Pandu Rangan (Nord. J. Comput., 1995)

An optimal parallel algorithm for the all-nearest-foreign-neighbors problem in arbitrary dimensions. - Thomas Graf; V. Kamakoti 001; N. S. Janaki Latha; C. Pandu Rangan (HiPC, 1997)

Efficient Algorithms for Prefix and General Prefix Computations on Distributed Shared Memory Systems with Applications. - V. Kamakoti 001; N. Balakrishnan 001 (ICPADS, 1997)

Sparse Dominance Queries for Many Points in Optimal Time and Space. - Thomas Graf; V. Kamakoti 001 (Inf. Process. Lett., 1997)

The Colored Sector Search Tree: A Dynamic Data Structure for Efficient High Dimensional Nearest-Foreign-Neighbor Queries. - Thomas Graf; V. Kamakoti 001; N. S. Janaki Latha; C. Pandu Rangan (COCOON, 1998)

Reducing Simple Polygons to Triangles - A Proof for an Improved Conjecture. - Thorsten Graf; Kamakoti Veezhinathan (ICALP, 1998)

An Optimal Algorithm for Computing Vissible Nearest Foreign Neighbors Among Colored Line Segments. - Thorsten Graf; Kamakoti Veezhinathan (SWAT, 1998)

Adaptive finite element analysis on a parallel and distributed environment. - V. Annamalai; C. S. Krishnamoorthy; V. Kamakoti 001 (Parallel Comput., 1999)

Toward Optimal Player Weights in Secure Distributed Protocols. - K. Srinathan 001; C. Pandu Rangan; V. Kamakoti 001 (INDOCRYPT, 2001)

A novel three phase parallel genetic approach to routing for field programmable gate arrays. - Annamalai Muthukaruppan; Sivaprakasam Suresh; V. Kamakoti 001 (FPT, 2002)

A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAs. - L. Kalyan Kumar; Amol J. Mupid; Aditya S. Ramani; V. Kamakoti 001 (Asian Test Symposium, 2003)

An enhanced evolutionary approach to spatial partitioning for reconfigurable environments. - Permandla Pratibha; Siva Nageswara Rao Borra; Annamalai Muthukaruppan; Sivaprakasam Suresh; V. Kamakoti 001 (IEEE Congress on Evolutionary Computation, 2003)

Testable Clock Routing Architecture for Field Programmable Gate Arrays. - L. Kalyan Kumar; Amol J. Mupid; Aditya S. Ramani; V. Kamakoti 001 (FPL, 2003)

Parallel Partitioning Techniques for Logic Minimization Using Redundancy Identification. - B. Jayaram 002; A. Manoj Kumar; V. Kamakoti 001 (HiPC, 2003)

A Parallel Evolutionary Approach to Spatial Partitioning in Reconfigurable Environments. - Permandla Pratibha; Siva Nageswara Rao Borra; Annamalai Muthukaruppan; Sivaprakasam Suresh; V. Ganesh; V. Kamakoti 001 (IICAI, 2003)

A Parallel Genetic Approach to the Placement Problem for Field Programmable Gate Arrays. - Siva Nageswara Rao Borra; Annamalai Muthukaruppan; Sivaprakasam Suresh; V. Kamakoti 001 (IPDPS, 2003)

Dynamic Coding Technique For Low-Power Data Bus. - M. Madhu; V. Srinivasa Murty; V. Kamakoti 001 (ISVLSI, 2003)

On-Line Location of Multiple Faults in LUT Based Reconfigurable Systems. - L. Kalyan Kumar; Aditya S. Ramani; Amol J. Mupid; V. Kamakoti 001; Sivaprakasam Suresh (VLSI, 2003)

MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis. - A. Manoj Kumar; Jayaram Bobba; V. Kamakoti 001 (DATE, 2004)

SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis. - A. Manoj Kumar; B. Jayaram 002; V. Kamakoti 001 (FPGA, 2004)

MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks. - R. Manimegalai; A. Manoj Kumar; B. Jayaram 002; V. Kamakoti 001 (FPL, 2004)

SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis. - R. Manimegalai; B. Jayaram 002; A. Manoj Kumar; V. Kamakoti 001 (FPT, 2004)

A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs. - E. Syam Sundar Reddy; Vikram Chandrasekhar; Milagros Sashikánth; V. Kamakoti 001; Vijaykrishnan Narayanan (FPT, 2004)

Face Recognition Using Weighted Modular Principle Component Analysis. - A. Pavan Kumar; Sukhendu Das; V. Kamakoti 001 (ICONIP, 2004)

A Hardware-Directed Face Recognition System Based on Local Eigen-analysis with PCNN. - Chakka Siva Sai Prasanna; N. Sudha; V. Kamakoti 001 (ICONIP, 2004)

An Architecture for Real Time Face Recognition Using WMPCA. - A. Pavan Kumar; V. Kamakoti 001; Sukhendu Das (ICVGIP, 2004)

MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Arrays. - A. Manoj Kumar; B. Jayaram 002; R. Manimegalai; V. Kamakoti 001 (IPDPS, 2004)

An Evolutionary Algorithm for Automatic Spatial Partitioning in Reconfigurable Environments. - Permandla Pratibha; Siva Nageswara Rao Borra; Annamalai Muthukaruppan; Sivaprakasam Suresh; V. Kamakoti 001 (MICAI, 2004)

A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation. - Kavish Seth; P. Rangarajan; S. Srinivasan 001; V. Kamakoti 001; V. Bala Kuteshwar (VLSI Design, 2004)

A Bus Encoding Technique for Power and Cross-talk Minimization. - P. Subrahmanya; R. Manimegalai; V. Kamakoti 001; Madhu Mutyam (VLSI Design, 2004)

A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. - Vivek Garg; Vikram Chandrasekhar; Milagros Sashikánth; V. Kamakoti 001 (ASP-DAC, 2005)

A function generator-based reconfigurable system. - Vivek Garg; Vikram Chandrasekhar; Milagros Sashikánth; V. Kamakoti 001 (ASP-DAC, 2005)

Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. - E. Syam Sundar Reddy; Vikram Chandrasekhar; Milagros Sashikánth; V. Kamakoti 001; Narayanan Vijaykrishnan (ASP-DAC, 2005)

A Framework for Automatic Assembly Program Generator (A2PG) for Verification and Testing of Processor Cores. - K. Uday Bhaskar; M. Prasanth; V. Kamakoti 001; Kailasnath Maneparambil (Asian Test Symposium, 2005)

FPGA based Agile Algorithm-On-Demand Co-Processor. - Ramachandran Pradeep; S. Vinay; Sanjay Burman; V. Kamakoti 001 (DATE, 2005)

Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). - E. Syam Sundar Reddy; Vikram Chandrasekhar; Milagros Sashikánth; V. Kamakoti 001; Narayanan Vijaykrishnan (FPGA, 2005)

Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs. - E. Syam Sundar Reddy; Vikram Chandrasekhar; Milagros Sashikánth; V. Kamakoti 001; Narayanan Vijaykrishnan (IPDPS, 2005)

A Universal Random Test Generator for Functional Verification of Microprocessors and System-on-Chip. - K. Uday Bhaskar; M. Prasanth; G. Chandramouli; V. Kamakoti 001 (VLSI Design, 2005)

Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines. - R. Manimegalai; E. Siva Soumya; Vaishnavi Muralidharan; Balaraman Ravindran; V. Kamakoti 001; Dinesh Bhatia (VLSI Design, 2005)

A Principal Component Neural Network-Based Face Recognition System and Its ASIC Implementation. - Chakka Siva Sai Prasanna; N. Sudha; V. Kamakoti 001 (VLSI Design, 2005)

Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. - E. Syam Sundar Reddy; Vikram Chandrasekhar; Milagros Sashikánth; V. Kamakoti 001; Narayanan Vijaykrishnan (VLSI Design, 2005)

Pseudo-online testing methodologies for various components of field programmable gate arrays. - L. Kalyan Kumar; Aditya S. Ramani; Amol J. Mupid; V. Kamakoti 001 (Microprocess. Microsystems, 2005)

Delay and peak power minimization for on-chip buses using temporal redundancy. - K. Najeeb; Vishal Gupta; V. Kamakoti 001; Madhu Mutyam (ACM Great Lakes Symposium on VLSI, 2006)

An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. - Vivek Garg; Vikram Chandrasekhar; Milagros Sashikánth; V. Kamakoti 001 (VLSI Design, 2006)

Ultra Folded High-Speed Architectures for Reed-Solomon Decoders. - Kavish Seth; K. N. Viswajith; S. Srinivasan 001; V. Kamakoti 001 (VLSI Design, 2006)

On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. - V. R. Devanathan; C. P. Ravikumar; V. Kamakoti 001 (J. Low Power Electron., 2006)

Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. - K. Najeeb; Vishal Gupta; V. Kamakoti 001; Madhu Mutyam (J. Low Power Electron., 2006)

Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. - V. R. Devanathan; C. P. Ravikumar; V. Kamakoti 001 (DATE, 2007)

LFSR Based Stream Ciphers Are Vulnerable to Power Attacks. - Sanjay Burman; Debdeep Mukhopadhyay; Kamakoti Veezhinathan (INDOCRYPT, 2007)

A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test. - V. R. Devanathan; C. P. Ravikumar; V. Kamakoti 001 (ITC, 2007)

PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. - V. R. Devanathan; C. P. Ravikumar; Rajat Mehrotra; V. Kamakoti 001 (ITC, 2007)

Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. - V. R. Devanathan; C. P. Ravikumar; V. Kamakoti 001 (VLSI Design, 2007)

Controllability-driven Power Virus Generation for Digital Circuits. - K. Najeeb; Karthik Gururaj; V. Kamakoti 001; Vivekananda M. Vedula (VLSI Design, 2007)

Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. - V. R. Devanathan; C. P. Ravikumar; V. Kamakoti 001 (VTS, 2007)

Power Virus Generation Using Behavioral Models of Circuits. - K. Najeeb; Vishnu Vardhan Reddy Konda; Siva Kumar Sastry Hari; V. Kamakoti 001; Vivekananda M. Vedula (VTS, 2007)

A novel approach to the placement and routing problems for field programmable gate arrays. - Siva Nageswara Rao Borra; Annamalai Muthukaruppan; Sivaprakasam Suresh; V. Kamakoti 001 (Appl. Soft Comput., 2007)

Variation-Tolerant, Power-Safe Pattern Generation. - V. R. Devanathan; C. P. Ravikumar; V. Kamakoti 001 (IEEE Des. Test Comput., 2007)

Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits. - K. Najeeb; Karthik Gururaj; V. Kamakoti 001; Vivekananda M. Vedula (J. Low Power Electron., 2007)

System-on-programmable-chip implementation for on-line face recognition. - A. Pavan Kumar; V. Kamakoti 001; Sukhendu Das (Pattern Recognit. Lett., 2007)

A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. - V. R. Devanathan; C. P. Ravikumar; Rajat Mehrotra; V. Kamakoti 001 (J. Low Power Electron., 2008)

Automatic Constraint Based Test Generation for Behavioral HDL Models. - Siva Kumar Sastry Hari; Vishnu Vardhan Reddy Konda; V. Kamakoti 001; Vivekananda M. Vedula; K. S. Maneperambil (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Efficient Grouping of Fail Chips for Volume Yield Diagnostics. - Lavanya Jagan; Ratan Deep Singh; V. Kamakoti 001; Ananta K. Majhi (VLSI Design, 2009)

Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures. - George Kurian; Narayana Rao; Virendra Patidar; V. Kamakoti 001; Srivaths Ravi 001 (J. Low Power Electron., 2009)

Novel SAT-Based Peak Dynamic Power Estimation for Digital Circuits. - K. Shyamala; J. Vimalkumar; V. Kamakoti 001 (J. Low Power Electron., 2009)

HTM design spaces: complete decoupling from caches and achieving highly concurrent transactions. - Kunal Korgaonkar; K. George; M. Gautam; V. Kamakoti 001 (ACM SIGOPS Oper. Syst. Rev., 2009)

Impact of Temperature on Test Quality. - Lavanya Jagan; Camelia Hora; Bram Kruseman; Stefan Eichenberger; Ananta K. Majhi; V. Kamakoti 001 (VLSI Design, 2010)

Efficient Motion Vector Recovery Algorithm for H.264 Using B-Spline Approximation. - Kavish Seth; V. Kamakoti 001; S. Srinivasan 001 (IEEE Trans. Broadcast., 2010)

Constructing Online Testable Circuits Using Reversible Logic. - Sk. Noor Mahammad; Kamakoti Veezhinathan (IEEE Trans. Instrum. Meas., 2010)

Reconstructing Hardware Transactional Memory for Workload Optimized Systems. - Kunal Korgaonkar; Prabhat Jain; Deepak Tomar; Kashyap Garimella; Veezhinathan Kamakoti (APPT, 2011)

Towards Quick Solutions for Generalized Placement Problem. - S. Srinivasan 001; V. Kamakoti 001; A. Bhattacharya (ISED, 2011)

A Method for Integrating Network-on-Chip Topologies with 3D ICs. - M. Pawan Kumar; Anish S. Kumar; Srinivasan Murali; Luca Benini; Kamakoti Veezhinathan (ISVLSI, 2011)

A Simulation Based Buffer Sizing Algorithm for Network on Chips. - Anish S. Kumar; M. Pawan Kumar; Srinivasan Murali; V. Kamakoti 001; Luca Benini; Giovanni De Micheli (ISVLSI, 2011)

Post-Synthesis Circuit Techniques for Runtime Leakage Reduction. - Seetal Potluri; Nitin Chandrachoodan; V. Kamakoti 001 (ISVLSI, 2011)

Hardware based genetic evolution of self-adaptive arbitrary response FIR filters. - Shoaib Mohammed; Sk. Noor Mahammad; V. Kamakoti 001 (Appl. Soft Comput., 2011)

ROSY: recovering processor and memory systems from hard errors. - Karthik Raghavan; V. Kamakoti 001 (ACM SIGOPS Oper. Syst. Rev., 2011)

The Implications of Shared Data Synchronization Techniques on Multi-Core Energy Efficiency. - Ashok Gautham; Kunal Korgaonkar; Patanjali SLPSK; Shankar Balachandran; Kamakoti Veezhinathan (HotPower, 2012)

A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands. - Anish S. Kumar; M. Pawan Kumar; Srinivasan Murali; V. Kamakoti 001; Luca Benini; Giovanni De Micheli (J. Electr. Comput. Eng., 2012)

Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs. - Rama Kumar Pasumarthi; V. R. Devanathan; V. Visvanathan; Seetal Potluri; V. Kamakoti 001 (J. Low Power Electron., 2012)

Interconnect Aware Test Power Reduction. - Seetal Potluri; Nitin Chandrachoodan; V. Kamakoti 001 (J. Low Power Electron., 2012)

Using timers to switch-off TCAM banks in routers. - Shankar Raman; Kamakoti Veezhinathan; Balaji Venkat; Gaurav Raina (IEEE ANTS, 2013)

PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information. - Seetal Potluri; Satya Trinadh; Roopashree Baskaran; Nitin Chandrachoodan; V. Kamakoti 001 (ETS, 2013)

A syllable based statistical text to speech system. - Abhijit Pradhan; S. Aswin Shanmugam; Anusha Prakash 001; Kamakoti Veezhinathan; Hema A. Murthy (EUSIPCO, 2013)

A Novel Algorithm for Fast Synthesis of DNA Probes on Microarrays. - Shri K. V. Srinivasan; V. Kamakoti 001; A. Bhattacharya (ACM J. Emerg. Technol. Comput. Syst., 2013)

Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions. - Virat Gandhi; V. R. Devanathan; V. Visvanathan; Milan Patnaik; V. Kamakoti 001 (J. Low Power Electron., 2013)

An Efficient Heuristic for Peak Capture Power Minimization During Scan-Based Test. - Satya Trinadh; Seetal Potluri; Ch. Sobhan Babu; V. Kamakoti 001 (J. Low Power Electron., 2013)

ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs. - Neel Gala; V. R. Devanathan; Karthik Srinivasan; V. Visvanathan; V. Kamakoti 001 (VLSID, 2014)

ReMap: A Novel Automated Peephole Optimization Based Approach for Logic, Delay and Power Minimization. - K. Shyamala; V. Kamakoti 001 (J. Low Power Electron., 2014)

XStat: Statistical X-Filling Algorithm for Peak Capture Power Reduction in Scan Tests. - Satya Trinadh; Seetal Potluri; Shankar Balachandran; Ch. Sobhan Babu; V. Kamakoti 001 (J. Low Power Electron., 2014)

SHAKTI-F: A Fault Tolerant Microprocessor Architecture. - Sukrat Gupta; Neel Gala; G. S. Madhusudan; V. Kamakoti 001 (ATS, 2015)

DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan tests. - Satya Trinadh; Ch. Sobhan Babu; Shiv Govind Singh; Seetal Potluri; V. Kamakoti 001 (DATE, 2015)

Framework for Selective Flip-Flop Replacement for Soft Error Mitigation. - Pavan Vithal Torvi; V. R. Devanathan; V. Kamakoti 001 (VLSID, 2015)

Generating synthetic benchmark circuits for accelerated life testing of field programmable gate arrays using genetic algorithm and particle swarm optimization. - L. Srivani; N. H. V. Krishna Giri; Shankar Ganesh; V. Kamakoti 001 (Appl. Soft Comput., 2015)

ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors. - Milan Patnaik; Chidhambaranathan Rajamanikkam; Chirag Garg; Arnab Roy 003; V. R. Devanathan; Shankar Balachandran; V. Kamakoti 001 (ACM J. Emerg. Technol. Comput. Syst., 2015)

Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications. - Neel Gala; V. R. Devanathan; V. Visvanathan; V. Kamakoti 001 (J. Low Power Electron., 2015)

DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing. - Seetal Potluri; Satya Trinadh; Ch. Sobhan Babu; V. Kamakoti 001; Nitin Chandrachoodan (ACM Trans. Design Autom. Electr. Syst., 2015)

Component fault localization using switching current measurements. - Seetal Potluri; Satya Trinadh; Siddhant Saraf; Kamakoti Veezhinathan (ETS, 2016)

STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection. - Neel Gala; Swagath Venkataramani; Anand Raghunathan; V. Kamakoti 001 (ISLPED, 2016)

ChADD: An ADD Based Chisel Compiler with Reduced Syntactic Variance. - Vikas Chauhan; Neel Gala; V. Kamakoti 001 (VLSID, 2016)

SHAKTI Processors: An Open-Source Hardware Initiative. - Neel Gala; Arjun Menon; Rahul Bodduna; G. S. Madhusudan; V. Kamakoti 001 (VLSID, 2016)

ProMAC: A proactive model predictive control based MAC protocol for cognitive radio vehicular networks. - N. Sathya Narayanan; Milan Patnaik; V. Kamakoti 001 (Comput. Commun., 2016)

Power Consumption versus Hardware Security: Feasibility Study of Differential Power Attack on Linear Feedback Shift Register Based Stream Ciphers and Its Countermeasures. - Sanjay Burman; Seetal Potluri; Debdeep Mukhopadhyay; Kamakoti Veezhinathan (J. Low Power Electron., 2016)

A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips. - Gokulkrishnan Vadakkeveedu; V. Kamakoti 001; Nitin Chandrachoodan; Seetal Potluri (DFT, 2017)

Shakti-T: A RISC-V Processor with Light Weight Security Extensions. - Arjun Menon; Subadra Murugan; Chester Rebeiro; Neel Gala; Kamakoti Veezhinathan (HASP@ISCA, 2017)

A Programmable Event-driven Architecture for Evaluating Spiking Neural Networks. - Arnab Roy 003; Swagath Venkataramani; Neel Gala; Sanchari Sen; Kamakoti Veezhinathan; Anand Raghunathan (ISLPED, 2017)

Optimal Don't Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing. - Satya Trinadh Adireddy; Seetal Potluri; Ch. Sobhan Babu; Veezhinathan Kamakoti; Shiv Govind Singh (ACM Trans. Design Autom. Electr. Syst., 2017)

Approximate Error Detection With Stochastic Checkers. - Neel Gala; Swagath Venkataramani; Anand Raghunathan; V. Kamakoti 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

ApproxBC: Blockchain Design Alternatives for Approximation-Tolerant Resource-Constrained Applications. - Prasanna Karthik Vairam; Gargi Mitra; Chester Rebeiro; Byrav Ramamurthy; Kamakoti Veezhinathan (IEEE Commun. Stand. Mag., 2018)

GANDALF: A Fine-Grained Hardware-Software Co-Design for Preventing Memory Attacks. - Gnanambikai Krishnakumar; Patanjali SLPSK; Prasanna Karthik Vairam; Chester Rebeiro; Kamakoti Veezhinathan (IEEE Embed. Syst. Lett., 2018)

An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators. - Neel Gala; Sarada Krithivasan; Wei-Yu Tsai; Xueqing Li 002; Vijaykrishnan Narayanan; V. Kamakoti 001 (ACM J. Emerg. Technol. Comput. Syst., 2018)

MLTimer: Leakage Power Minimization in Digital Circuits Using Machine Learning and Adaptive Lazy Timing Analysis. - Patanjali SLPSK; Milan Patnaik; Seetal Potluri; V. Kamakoti 001 (J. Low Power Electron., 2018)

Towards Identifying Early Indicators of a Malware Infection. - Sareena Karapoola; Chester Rebeiro; Unnati Parekh; Kamakoti Veezhinathan (AsiaCCS, 2019)

Karna: A Gate-Sizing based Security Aware EDA Flow for Improved Power Side-Channel Attack Protection. - Patanjali SLPSK; Prasanna Karthik Vairam; Chester Rebeiro; V. Kamakoti 001 (ICCAD, 2019)

Towards Measuring Quality of Service in Untrusted Multi-Vendor Service Function Chains: Balancing Security and Resource Consumption. - Prasanna Karthik Vairam; Gargi Mitra; Vignesh Manoharan; Chester Rebeiro; Byrav Ramamurthy; Kamakoti Veezhinathan (INFOCOM, 2019)

SHAKTI-MS: a RISC-V processor for memory safety in C. - Sourav Das; R. Harikrishnan Unnithan; Arjun Menon; Chester Rebeiro; Kamakoti Veezhinathan (LCTES, 2019)

White Mirror: Leaking Sensitive Information from Interactive Netflix Movies using Encrypted Traffic Analysis. - Gargi Mitra; Prasanna Karthik Vairam; Patanjali SLPSK; Nitin Chandrachoodan; Kamakoti Veezhinathan (SIGCOMM Posters and Demos, 2019)

PERI: A Posit Enabled RISC-V Core. - Sugandha Tiwari; Neel Gala; Chester Rebeiro; V. Kamakoti 001 (CoRR, 2019)

PROLEMus: A Proactive Learning-Based MAC Protocol Against PUEA and SSDF Attacks in Energy Constrained Cognitive Radio Networks. - Milan Patnaik; V. Kamakoti 001; Vashek Matyas; Vojtech Rehák (IEEE Trans. Cogn. Commun. Netw., 2019)

VNF-DOC: A Dynamic Overload Controller for Virtualized Network Functions in Cloud. - Sudhakar Murugasen; Shankar Raman; Kamakoti Veezhinathan (AINA, 2020)

Sparsity-Aware Caches to Accelerate Deep Neural Networks. - Vinod Ganesan; Sanchari Sen; Pratyush Kumar; Neel Gala; Kamakoti Veezhinathan; Anand Raghunathan (DATE, 2020)

Depending on HTTP/2 for Privacy? Good Luck! - Gargi Mitra; Prasanna Karthik Vairam; Patanjali SLPSK; Nitin Chandrachoodan; Kamakoti Veezhinathan (DSN, 2020)

Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER. - Rahul Bodduna; Vinod Ganesan; Patanjali SLPSK; Kamakoti Veezhinathan; Chester Rebeiro (IEEE Comput. Archit. Lett., 2020)

Net-Police: A network patrolling service for effective mitigation of volumetric DDoS attacks. - Sareena Karapoola; Prasanna Karthik Vairam; Shankar Raman; Veezhinathan Kamakoti (Comput. Commun., 2020)

ProBLeSS: A Proactive Blockchain Based Spectrum Sharing Protocol Against SSDF Attacks in Cognitive Radio IoBT Networks. - Milan Patnaik; G. Prabhu; Chester Rebeiro; Vashek Matyas; Kamakoti Veezhinathan (IEEE Netw. Lett., 2020)

Scalable pseudo-exhaustive methodology for testing and diagnosis in flow-based microfluidic biochips. - Gokulkrishnan Vadakkeveedu; Kamakoti Veezhinathan; Nitin Chandrachoodan; Seetal Potluri (IET Comput. Digit. Tech., 2020)

PERI: A Configurable Posit Enabled RISC-V Core. - Sugandha Tiwari; Neel Gala; Chester Rebeiro; V. Kamakoti 001 (ACM Trans. Archit. Code Optim., 2021)

RaDaR: A Real-Word Dataset for AI powered Run-time Detection of Cyber-Attacks. - Sareena Karapoola; Nikhilesh Singh; Chester Rebeiro; V. Kamakoti 001 (CIKM, 2022)

JUGAAD: Comprehensive Malware Behavior-as-a-Service. - Sareena Karapoola; Nikhilesh Singh; Chester Rebeiro; Kamakoti Veezhinathan (CSET @ USENIX Security Symposium, 2022)

Building the SHAKTI microprocessor. - Kamakoti Veezhinathan (Commun. ACM, 2022)

FadingBF: A Bloom Filter With Consistent Guarantees for Online Applications. - Prasanna Karthik Vairam; Pratyush Kumar; Chester Rebeiro; V. Kamakoti 001 (IEEE Trans. Computers, 2022)

YODA: Covert Communication Channel over Public DNS Resolvers. - Sandip Saha; Sareena Karapoola; Chester Rebeiro; V. Kamakoti 001 (DSN, 2023)

iPyrDAE: Image Pyramid-Based Denoising Autoencoder for Infrared Breast Images. - Kaushik Raghavan; B. Sivaselavan; V. Kamakoti 001 (PReMI, 2023)

Snoopy: A Webpage Fingerprinting Framework With Finite Query Model for Mass-Surveillance. - Gargi Mitra; Prasanna Karthik Vairam; Sandip Saha; Nitin Chandrachoodan; V. Kamakoti 001 (IEEE Trans. Dependable Secur. Comput., 2023)

Explainable artificial intelligence for medical imaging: Review and experiments with infrared breast images. - Kaushik Raghavan; Sivaselvan Balasubramanian; Kamakoti Veezhinathan (Comput. Intell., 2024)

SUNDEW: A Case-Sensitive Detection Engine to Counter Malware Diversity. - Sareena Karapoola; Nikhilesh Singh; Chester Rebeiro; Kamakoti Veezhinathan (IEEE Trans. Dependable Secur. Comput., 2025)