Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration. - Tadeu Mota Frutuoso; Xavier Garros; Perrine Batude; Laurent Brunet; Joris Lacord; Benoit Sklénard; V. Lapras; Claire Fenouillet-Béranger; M. Ribotta; A. Magalhaes-Lucas; J. Kanyandekwe; R. Kies; et al. (VLSI Technology and Circuits, 2022)

First Radio-Frequency Circuits Fabricated in Top-Tier of a Full 3D Sequential Integration Process at mmW for 5G Applications. - J. Luge-Alvarez; J. B. David; Alexandre Siligaris; Vincent Puyal; G. Moritz; Tadeu Mota Frutuoso; V. Lapras; Claire Fenouillet-Béranger; Laurent Brunet; P. Vincent; Didier Lattard; Xavier Garros; et al. (VLSI Technology and Circuits, 2024)

Fast CV MSM Technique for Comprehensive Analysis of Bulk Trapping in Low-K Carbon-Doped Dielectrics. - Tadeu Mota Frutuoso; William Vandendaele; A. Bond; F. Bringuier; V. Lapras; Marie Claire Cyrille; Claire Fenouillet-Béranger; B. Duriez; Xavier Garros (IRPS, 2025)