Design of Novel SRAM Cell Using Hybrid VLSI Techniques for Low Leakage and High Speed in Embedded Memories. - K. Gavaskar; U. S. Ragupathy 001; V. Malini (Wirel. Pers. Commun., 2019)

Proposed Design of 1 KB Memory Array Structure for Cache Memories. - K. Gavaskar; U. S. Ragupathy 001; V. Malini (Wirel. Pers. Commun., 2019)