An optimized BIST test pattern generator for delay testing. - Patrick Girard 001; Christian Landrault; V. Moreda; Serge Pravossoudovitch (VTS, 1997)

A BIST Structure to Test Delay Faults in a Scan Environment. - Patrick Girard 001; Christian Landrault; V. Moreda; Serge Pravossoudovitch; Arnaud Virazel (Asian Test Symposium, 1998)

A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. - Patrick Girard 001; Christian Landrault; V. Moreda; Serge Pravossoudovitch; Arnaud Virazel (J. Electron. Test., 1999)