Analysis of microbump induced stress effects in 3D stacked IC technologies. - Andrej Ivankovic; Geert Van der Plas; V. Moroz; M. Choi; Vladimir Cherman; Abdelkarim Mercha; Paul Marchal; Marcel Gonzalez; Geert Eneman; Wenqi Zhang; Thibault Buisson; Mikael Detalle; et al. (3DIC, 2011)

An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations. - Geert Eneman; J. Cho; V. Moroz; Dragomir Milojevic; M. Choi; Kristin De Meyer; Abdelkarim Mercha; Eric Beyne; Thomas Hoffmann 001; Geert Van der Plas (DATE, 2011)

Through silicon via to FinFET noise coupling in 3-D integrated circuits. - A. Rouhi Najaf Abadi; W. Guo; X. Sun; K. Ben Ali; Jean-Pierre Raskin; Martin Rack; C. Roda Neve; M. Choi; V. Moroz; Geert Van der Plas; Ingrid De Wolf; Eric Beyne; et al. (ICICDT, 2015)