A Framework for Concurrency Control in Real-Time Distributed Collaboration for Mobile Systems. - D. Janaki Ram; M. A. Maluk Mohamed; V. R. Devanathan (ICDCS Workshops, 2003)

Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage. - V. R. Devanathan (Asian Test Symposium, 2005)

A Framework for Distributed and Hierarchical Design-for-Test. - C. P. Ravikumar; R. Dandamudi; V. R. Devanathan; N. Haldar; K. Kiran; P. S. Vijay Kumar (VLSI Design, 2005)

On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. - V. R. Devanathan; C. P. Ravikumar; V. Kamakoti 001 (J. Low Power Electron., 2006)

Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. - V. R. Devanathan; C. P. Ravikumar; V. Kamakoti 001 (DATE, 2007)

Methodology for low power test pattern generation using activity threshold control logic. - Srivaths Ravi 001; V. R. Devanathan; Rubin A. Parekhji (ICCAD, 2007)

A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test. - V. R. Devanathan; C. P. Ravikumar; V. Kamakoti 001 (ITC, 2007)

PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. - V. R. Devanathan; C. P. Ravikumar; Rajat Mehrotra; V. Kamakoti 001 (ITC, 2007)

Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. - V. R. Devanathan; C. P. Ravikumar; V. Kamakoti 001 (VLSI Design, 2007)

Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. - V. R. Devanathan; C. P. Ravikumar; V. Kamakoti 001 (VTS, 2007)

Variation-Tolerant, Power-Safe Pattern Generation. - V. R. Devanathan; C. P. Ravikumar; V. Kamakoti 001 (IEEE Des. Test Comput., 2007)

A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. - V. R. Devanathan; C. P. Ravikumar; Rajat Mehrotra; V. Kamakoti 001 (J. Low Power Electron., 2008)

Towards effective and compression-friendly test of memory interface logic. - V. R. Devanathan; Alan Hales; Sumant Kale; Dharmesh Sonkar (ITC, 2010)

EOMP: an exactly once multicast protocol for distributed mobile systems. - M. A. Maluk Mohamed; V. R. Devanathan; D. Janakiram (Int. J. Parallel Emergent Distributed Syst., 2010)

Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCs. - V. R. Devanathan; Sunil Bhavsar; Rajat Mehrotra (Asian Test Symposium, 2011)

Techniques to improve memory interface test quality for complex SoCs. - V. R. Devanathan; Srinivas Kumar Vooka (ITC, 2011)

Hazard-Aware Directed Transition Fault ATPG for Effective Critical Path Test. - V. R. Devanathan; Ishaan Santhosh Shah (VLSI Design, 2011)

Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs. - Rama Kumar Pasumarthi; V. R. Devanathan; V. Visvanathan; Seetal Potluri; V. Kamakoti 001 (J. Low Power Electron., 2012)

Towards adaptive test of multi-core RF SoCs. - Rajesh Mittal; Lakshmanan Balasubramanian; Y. B. Chethan Kumar; V. R. Devanathan; Mudasir Kawoosa; Rubin A. Parekhji (DATE, 2013)

Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions. - Virat Gandhi; V. R. Devanathan; V. Visvanathan; Milan Patnaik; V. Kamakoti 001 (J. Low Power Electron., 2013)

ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs. - Neel Gala; V. R. Devanathan; Karthik Srinivasan; V. Visvanathan; V. Kamakoti 001 (VLSID, 2014)

New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation. - V. R. Devanathan; Lakshmanan Balasubramanian; Rubin A. Parekhji (VLSID, 2015)

Framework for Selective Flip-Flop Replacement for Soft Error Mitigation. - Pavan Vithal Torvi; V. R. Devanathan; V. Kamakoti 001 (VLSID, 2015)

ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors. - Milan Patnaik; Chidhambaranathan Rajamanikkam; Chirag Garg; Arnab Roy 003; V. R. Devanathan; Shankar Balachandran; V. Kamakoti 001 (ACM J. Emerg. Technol. Comput. Syst., 2015)

Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications. - Neel Gala; V. R. Devanathan; V. Visvanathan; V. Kamakoti 001 (J. Low Power Electron., 2015)

A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapath. - V. R. Devanathan; Sumant Kale (ITC, 2016)